abdelazeem201

ASIC-Design-Roadmap

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

ASIC-implementation-of-AES

Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The Verilog language is utilized for simulating the design and an fpga & ASIC chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput, and critical path delay.

ASIC-Implementation-UART

This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from system clock. If we increase the baud rate, speed of serial data transmission increases. As the dividing factor decrease baud rate increases. in this paper we set the system clock frequency as 50MHz and time to transfer each data bit is 23.75ns with baud rate of 42.1 Mbps (dividing factor is 32). Due to increase in the baud rate the time taken to transfer the data decreases, so it is very useful for faster communication devices. Transmitter and Receiver blocks designed by algorithm state machine method simulated in ModelSim, synthesized in Design Compiler, and extracted in ICC in Nangate 45 nm CMOS cell library.

Basic-Static-Timing-Analysis

Cadence-RTL-to-GDSII-Flow

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

ICC2_scripts

This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.

Introduction-to-System-on-Chip-Design-Online-Course

To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA platforms using standard hardware description and software programming languages

SoC-Implementation-of-OpenMSP430-Microcontroller

The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 microcontroller family. Due to its characteristics, the openMSP430 was selected to integrate the System on Chip (SOC). This open-core, that will be implemented as an Application Specific Integrated Circuit (ASIC), was previously synthesized, for a SAEDCMOS 90nm target technology process.

Systolic-array-implementation-in-RTL-for-TPU

IC implementation of Systolic Array for TPU

abdelazeem201/ASIC-Design-Roadmap

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU

IC implementation of Systolic Array for TPU

abdelazeem201/Cadence-RTL-to-GDSII-Flow

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

abdelazeem201/ICC2_scripts

This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.

abdelazeem201/RTL-to-Gates-Synthesis-using-Synopsys-tools

For this assignment, you will become familiar with the VLSI tools you will use throughout this semester, learn how a design “flows” through the toolflow, and practice Verilog coding. Specifically, you will write an RTL model of a GCD circuit, synthesize and place and route the design, simulate at every stage, and analyze power.

abdelazeem201/Spiking-Neural-Processor

This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologically-inspired class of artificial neural networks, where neurons communicate by sending discrete spikes.

abdelazeem201/100daysofRTL

Every Day I will be uploading an RTL code with Synthesized Design and TB for RISC CPU Design

abdelazeem201/The-Power-of-TCL

abdelazeem201/APB-I2S

I2S (Inter-IC Sound) interface module with APB (Advanced Peripheral Bus) interface signals. It has control logic for writing and reading data to/from a 4x32-bit FIFO and generates clock (sck), word select (ws), and serial data (sd) signals for I2S transmission.

abdelazeem201/Resume

A one-page, one column resume template in LaTeX that caters particularly to an undergraduate ECE/CSE student.

abdelazeem201/abdelazeem201

abdelazeem201/CS250-Laboratory-1

For this assignment, you will become familiar with the VLSI tools you will use throughout this semester, learn how a design “flows” through the toolflow, and practice Verilog coding. Specifically, you will write an RTL model of a GCD circuit, synthesize and place and route the design, simulate at every stage, and analyze power.

abdelazeem201/abdelazeem201.github.io

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

abdelazeem201/DTMF

Design and Implementation of Goertzel Algorithm for DTMF application on ASIC.

abdelazeem201/hdmi

Send video/audio over HDMI on an FPGA

abdelazeem201/Machine-Learning-based-Domain-Specific-Hardware-Accelerators

Domain Specific Hardware Accelerators

abdelazeem201/open-eda-course

abdelazeem201/skywater130_scl_9T

skywater130_scl_9T for Synopsys and Cadence Flow

abdelazeem201/SoC-FPGA

System-on-a-Chip Field-Programmable Gate Array (SoC-FPGA)

abdelazeem201/VID_TIMING_GEN

Video Timing Generator

abdelazeem201/asap7_reference_design

reference block design for the ASAP7nm library in Cadence Innovus

abdelazeem201/ASIC-Implementation-of-Convolutional-Neural-Network-for-Real-Time-Application

ASIC Implementation of Convolutional Neural Network for Real-Time Application

abdelazeem201/awesome-palestine

A curated list of Palestine and Palestinian-Israeli conflict resources.

abdelazeem201/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

abdelazeem201/core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

abdelazeem201/Course

Course

abdelazeem201/DFT

abdelazeem201/OsvvmLibraries

Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

abdelazeem201/verilog-format

Verilog formatter