yosys -- Yosys Open SYnthesis Suite

Copyright (C) 2019 SCALE Lab, Brown University

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Original Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>

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// [[CITE]] ABC
// Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
// http://www.eecs.berkeley.edu/~alanmi/abc/

// [[CITE]] RePlAce
// UCSD VLSI CAD LABORATORY, RePlAce: A Global Placement tool
// https://github.com/abk-openroad/RePlAce

Physical yosys -- A Physical Flow Integration in Yosys

Physical yosys aims at improving the timing optimizaions of yosys/ABC through adding physical-awareness (along with other features) in the synthesis flow. Physical yosys in implemented by Scale Lab at Brown University as part of the OPENROAD project.

This is a fork and extension from open-source yosys tool as available here:

https://github.com/YosysHQ/yosys

Along with the standard functionality provided by yosys, Physical yosys aims to add support for physical aware logic synthesis, and better timing constraint handling through ABC.

The used ABC version is a forked and modified version that could be found here.

Physical Yosys along with Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license).

Website and Other Resources

For original yosys documentation and installation please refer to:

Getting Started with Physical-Synthesis

Overall, the functionality of Physical yosys is very closely similar to standard yosys with extra functionality added to the existing commands and some new commands.

Physical-aware gate sizing and buffering:

Physical yosys aims at enabling the integration of physical placement Information into logic optimizations.

Currently, physical yosys allows for this information to be used for gate sizing and buffering optimizations done inside ABC.

Physical yosys uses RePlAce for placement, a Verilog to Def Translator and a Pin Placer to generate post-placement wire capacitances. These wire capacitances are then passed in a spef file to ABC where the optimizations are performed. physical flow is Implemented as a phys_abc command as it relies on ABC to perform physical aware gate sizing and buffering, -clk_port flag must be set by the name of the used library flip-flop clock port, and if there are multiple clock ports all must be set by -clk_port clk1 -clk_port .... also to run the physical flow using RePlAce, the following arguments must be set:

For the def genetator: -DefGenerator needs to be set to the location of the def translator as well as the needed arguments used by the Def Translator as -defDbu, siteName, -die_width, -die_height, for more info about these arguments visit The Def Translator Gihub Repo
For the pins placer: -PinsPlacer needs to be set to the location of the pins placer, the metal layer on which the pins would be placed can be defined by the option -layer which should be an integer value, You can find the script here.
For RePlAce: -RePlAce needs to be set to the location to replace as well as the needed arguments used by RePlAce as -liberty, -constr, -res_per_micron, -cap_per_micron, -output, for more info about these arguments visit RePlAce Gihub Repo

More information can be found by looking at help phys_abc in yosys. An example use case is as follows.

read_verilog test.v

# the high-level stuff
synth -flatten

# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib

# mapping logic to mycells.lib
abc -liberty mycells.lib

# cleanup
opt_clean -purge

#enabling physical flow
phys_abc -liberty mycell s.lib -clk_port CLK -RePlAce ... -lef file1.lef -lef file2.lef -constr myfile.sdc
-res_per_micron 1.261261 -cap_per_micron 0.226596e-15 -output output -dpflag ... -dploc ... 
-PinsPlacer ... -DefGenerator ... -defDbu 2000 -siteName ... -die_width 42 -die_height 42

# another cleanup
opt_clean -purge

#writing output
write_verilog test_netlist.v

Timing Constraints Through SDC Files

Physical yosys has added support for SDC file parsing through synopsys open source sdc parser. The parser is integrated into ABC, enabling passing of timing constraints through standard sdc syntax.

This works with both abc and phys_abc commands.

Generally, Yosys itself doesn't use the SDC file, It just passes it to ABC, so the SDC parser can be enabled by one of two methods:

Through Yosys by adding the -s flag after the -constr flag in abc or phys_abc command, and Yosys will pass it to ABC.
Through ABC directly by adding -s flag to read_constr command in the ABC script.

If -s flag was not added, the typical constraints parser of ABC (non SDC) will be used.

A snippet of code demonstrating the use case of the SDC Parser in Yosys is as follows:

abc -liberty mycells.lib -script ${abc_script} -constr -s myfile.sdc

A snippet of code demonstrating the use case of the SDC Parser in ABC is as follows:

set constr_file myfile.sdc
set abc_script "+read_constr,-s,${constr_file};strash;ifraig;retime,-D,450,-M,6;strash;dch;map;"
abc -liberty mycells.lib -script ${abc_script}

Currently, while the parsing of all the sdc syntax is supported, due to limited support of ABC for timing constraints, very few timing constraints are realized by ABC, while the rest are mainly Ignored. The current list of supported timing constraints include:

create_clock        #Support for target clock period
set_max_fanout      #Support for global max fanout
set_max_transition  #Support for global target slew

We are working on adding support for other timing constraints in ABC.

Helper Scripts

Incremental DEF Writer Script

It takes Two Def files and Merge them while retaining the placement data found in the placed one.

Inputs:
1. DEF file with all the components Placed
2. The new DEF file with the modified/added components which are all unplaced
Output: DEF file with all components including Modified/Added ones from the second def files, with all components placed in the locations from the first placed DEF if found, else the component is placed in the centroid of its fanins and fanouts
Usage: python incremental_def_writer.py -placed placed.def -unplaced unplaced.def -output output.def
The Script could be found here.

Pins Placer Script

It takes a def file with the pins unplaced and place them around the die perimeter, It can also change the layer on which pins are placed through the option -layer which should be an integer value with the layer number.

Usage: python pins_placer.py -def file.def -output output.def [-layer layer_number]
The Script could be found here.

Demo Script

There is a demo script for the added options. This Demo runs Logic Synthesis then Physical Synthesis for the GCD benchmark using ASAP7 library files, more details can be found inside the script itself.

The Benchmark and the Library files can be found in the folder demo.

To run it this demo script:

Clone and build the repository.
Run the script using ./yosys demo/run_yosys_physical_synthesis.tcl.

The output netlist could be found at demo/output

Remark

This Repo is currently maintained by Marina Neseem marina_neseem@brown.edu. Consider also Soheil Hashemi soheil_hashemi@alumni.brown.edu who has started this effort.

abdelrahmanhosny/yosys