abdulhameed-akram

Engineer

Pinned Repositories

ArchBench
Architecture file validation testcase - RTL to Bitstream simulation flow
Language:Verilog00
Jira_Testcase
Language:Verilog00
Raptor
Raptor end-to-end FPGA Compiler and GUI
Language:Verilog00
Validation
Raptor Validation - New clean version of Compiler_Validation repo
Language:Verilog00
FOEDAG
Framework Open EDA Gui
Language:C++60 17 15229
IP_Catalog
IP Catalog for Raptor.
Language:Verilog9 4 28
Raptor
Raptor end-to-end FPGA Compiler and GUI
Language:Verilog65 6 6222
Validation
Raptor Compiler Validation tests
Language:Verilog2 2 015
iverilog
Icarus Verilog
Language:C++2.9k 134 721530
verilator
Verilator open-source SystemVerilog simulator and lint system
Language:C++2.6k 72 3.5k613

abdulhameed-akram's Repositories

abdulhameed-akram/ArchBench
Architecture file validation testcase - RTL to Bitstream simulation flow
Language:Verilog00
abdulhameed-akram/Jira_Testcase
Language:Verilog00
abdulhameed-akram/Raptor
Raptor end-to-end FPGA Compiler and GUI
Language:Verilog00
abdulhameed-akram/Validation
Raptor Validation - New clean version of Compiler_Validation repo
Language:Verilog00