Pinned Repositories
awesome-opensource-asic-resources
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
FIFOtest_repo
Simple repository to test versioning on Vivado
labtool
Software for the LabTool logic analyzer and oscilloscope
linux_setup
Wiki with some commands I use to configure a linux system to my own needs.
pulp-training
Exercises for PULP hands-on trainings
pulp_docs_abet
md documentation of pulp-platform environment
pulp_soc
pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
abettati's Repositories
abettati/awesome-opensource-asic-resources
abettati/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
abettati/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
abettati/FIFOtest_repo
Simple repository to test versioning on Vivado
abettati/labtool
Software for the LabTool logic analyzer and oscilloscope
abettati/linux_setup
Wiki with some commands I use to configure a linux system to my own needs.
abettati/pulp-training
Exercises for PULP hands-on trainings
abettati/pulp_docs_abet
md documentation of pulp-platform environment
abettati/pulp_soc
abettati/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
abettati/riscv_mirror2
abettati/riscv_old_mirror
abettati/template_mcu
Quick template for mcuxpresso and some workflow tests.
abettati/uvmprimer
Contains the code examples from The UVM Primer Book sorted by chapters.
abettati/VHDL-TestbenchGen
VHDL Testbench Generator