abhishek2002228
Student at BITS Pilani | Interested in all verticals of Computer Systems and VLSI Design
Pinned Repositories
Booksim_CADL
CacheSim
COMSOL_MEMS
DRUM_Approximate_Multiplier
Floating-Point-ALU
OSTEP_Projects
Pong_VGA
Pong game on the NexysA7-50T FPGA Board displayed using a VGA interface and written in Verilog
RISCV-Processors
RISCV_MYTH_CORE
RISCV-MYTH Core
uart-core
Basic UART RX/TX modules with FIFO interface for FPGA's
abhishek2002228's Repositories
abhishek2002228/RISCV_MYTH_CORE
RISCV-MYTH Core
abhishek2002228/DRUM_Approximate_Multiplier
abhishek2002228/OSTEP_Projects
abhishek2002228/Pong_VGA
Pong game on the NexysA7-50T FPGA Board displayed using a VGA interface and written in Verilog
abhishek2002228/RISCV-Processors
abhishek2002228/Booksim_CADL
abhishek2002228/CacheSim
abhishek2002228/COMSOL_MEMS
abhishek2002228/Floating-Point-ALU
abhishek2002228/Operating-Systems-Assignments
abhishek2002228/TicTacToe_Minimax
abhishek2002228/uart-core
Basic UART RX/TX modules with FIFO interface for FPGA's
abhishek2002228/verilog-1
Repository for basic (and not so basic) Verilog blocks with high re-use potential
abhishek2002228/chisel-template-1
A template project for beginning new Chisel work
abhishek2002228/Computer_Systems_Dir
abhishek2002228/Course_Notes_3rdYear
abhishek2002228/miscellaneous
abhishek2002228/Neural-Networks-Fuzzy-Logic
abhishek2002228/Verilog
A Working Directory to keep track of my learning process in Verilog HDL