Pinned Repositories
abukharmeh.github.io
ctagsx
VSCode ctags implementation that actually works
cv32e41p
4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
embecosm-toolchain-releases
llvm-project
PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
markdown-cheatsheet
Markdown Cheatsheet for Github Readme.md
mkgmap
Mirror of mkgmap's Subversion repository
newlib_cygwin
riscv-code-size-reduction
abukharmeh's Repositories
abukharmeh/abukharmeh.github.io
abukharmeh/ctagsx
VSCode ctags implementation that actually works
abukharmeh/cv32e41p
4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
abukharmeh/embecosm-toolchain-releases
abukharmeh/llvm-project
PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
abukharmeh/markdown-cheatsheet
Markdown Cheatsheet for Github Readme.md
abukharmeh/mkgmap
Mirror of mkgmap's Subversion repository
abukharmeh/newlib_cygwin
abukharmeh/programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
abukharmeh/riscv-code-size-reduction
abukharmeh/riscv-isa-manual
RISC-V Instruction Set Manual
abukharmeh/riscv-tests
abukharmeh/riscv-v-spec
Working draft of the proposed RISC-V V vector extension
abukharmeh/sail-riscv
Sail RISC-V model
abukharmeh/security
RISC-V Security HC admin repo
abukharmeh/uvm_demo1
Simple UVM for a cache.
abukharmeh/vscode-mips-support
abukharmeh/zce_toolchain_ci