Pinned Repositories
ALU
8-bit Arithmetic Logic Unit - Designed an ALU capable of addition, subtraction, NAND, XOR operations using behavioral VHDL • Implemented dataflow modelling; verified the design using testbench and performed scan chain testing
AudioVU
recipie
RISC
Designing a complete 6-bit RISC processor project involves significant complexity and detail, including multiple components like the instruction set, datapath, controller, and pipeline stages. Providing a full code implementation within this context is extensive and typically requires detailed specifications and design considerations.
adityavijayy's Repositories
adityavijayy/ALU
8-bit Arithmetic Logic Unit - Designed an ALU capable of addition, subtraction, NAND, XOR operations using behavioral VHDL • Implemented dataflow modelling; verified the design using testbench and performed scan chain testing
adityavijayy/AudioVU
adityavijayy/recipie
adityavijayy/RISC
Designing a complete 6-bit RISC processor project involves significant complexity and detail, including multiple components like the instruction set, datapath, controller, and pipeline stages. Providing a full code implementation within this context is extensive and typically requires detailed specifications and design considerations.