/SHA-1-VHDL

Implementation of SHA-1 core in VHDL for FPGA Using Pipeline

Primary LanguageVHDLOtherNOASSERTION

SHA-1-VHDL

Implementation of SHA-1 core in VHDL for FPGA Using Pipeline Technique

Here is listed a VHDL implementation of SHA-1. The design includes 2 parts a Padding which takes messages up to 55 characters and the SHA-1 core which processes the padded message. A testbench for the validation of the design is provided.