Pinned Repositories
-TAGE-based-Predictor-Verilog-Code
Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
adwait.github.io
My webpage
asplos24-micro-update-lifting
Companion artifact for ASPLOS '24: Lifting Micro-Update Models from RTL
AutoSlides
btor2opt
Very basic btor2 parser, circuit miter, and code optimizer
llvmlite-dataflow
Generate dataflow graphs with the llvmlite Python library
PS2SC
Bounded model checker for PS 2.0
pyclid
Python wrapper for UCLID5
VossII
The source code to the Voss II Hardware Verification Suite
uclid
UCLID5: formal modeling, verification, and synthesis of computational systems
adwait's Repositories
adwait/asplos24-micro-update-lifting
Companion artifact for ASPLOS '24: Lifting Micro-Update Models from RTL
adwait/pyclid
Python wrapper for UCLID5
adwait/btor2opt
Very basic btor2 parser, circuit miter, and code optimizer
adwait/PS2SC
Bounded model checker for PS 2.0
adwait/VossII
The source code to the Voss II Hardware Verification Suite
adwait/-TAGE-based-Predictor-Verilog-Code
Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
adwait/adwait.github.io
My webpage
adwait/AutoSlides
adwait/axiomatic-operational-examples
Experimental examples for axiomatic-operational
adwait/axiomatix
adwait/daikon
Dynamic detection of likely invariants
adwait/DB-Project
Parallel join optimisation scheme for PostgreSQL
adwait/llvmlite-dataflow
Generate dataflow graphs with the llvmlite Python library
adwait/multi_vscale
Verilog version of Z-scale (deprecated)
adwait/btor2ex
Barebones symex and model-checking for BTOR2
adwait/c3-simulator
C3-Simulator is a Simics-based functional simulator for the X86 C3 processor, including library and kernel support for pointer and data encryption, stack unwinding support for C++ exception handling, debugger enabling, and scripting for running tests.
adwait/Deterministic_Model
Deterministic_Models
adwait/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
adwait/pyeda
Python EDA
adwait/pyvcd
Python package for writing Value Change Dump (VCD) files.
adwait/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
adwait/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
adwait/riscv-sodor
educational microarchitectures for risc-v isa
adwait/sdram-controller
Verilog SDRAM memory controller
adwait/syncuit
circuit problem synthesis
adwait/Tomasulo-Machine
adwait/uclid
UCLID5: formal modeling, verification, and synthesis of computational systems
adwait/webpage-generator
A simple script to generate a clean academic webpage (courtesy: Federico)
adwait/zipcpu
A small, light weight, RISC CPU soft core
adwait/zsim
A fast and scalable x86-64 multicore simulator