Pipelined Processor

A 5-stage pipelined processor with a RISC-like instruction set architecture., Harvard Architecture.

About

Specs

  • Eight 4-byte general purpose registers; R0, till R7
  • Two general purpose registers, a program counter (PC) and a stack pointer (SP)
  • Memory address space is 1 MB of 16-bit width and is word addressable
  • Detection and stalling in case of Load-Use
  • Full Forwarding for Data Hazards
  • Two memories to solve Structural Hazards

Pipelined-processor

Pipelined-processor

Pipelined-processor