Implementing 32 Verilog Mini Projects.
32 bit adder,
Array Multiplier,
Barrel Shifter,
Binary Divider 16 by 8,
Booth Multiplication,
CRC Coding,
Carry Select and Carry Look Ahead Adder,
Carry Skip and Carry Save Adder,
Complex Multiplier,
Dice Game,
FIFO,
Fixed Point Adder and Subtractor,
Fixed Point Multiplier and Divider,
Floating Point IEEE 754 Addition Subtraction,
Floating Point IEEE 754 Division,
Floating Point IEEE 754 Multiplication,
Fraction Multiplier,
High Radix Multiplier,
I2C and SPI Protocols,
LFSR and CFSR,
Logarithm Implementation,
Mealy and Moore State Machine Implementation of Sequence Detector,
Modified Booth Algorithm,
Pipelined Multiplier,
Restoring and Non Restoring Division,
Sequential Multiplier,
Shift and Add Binary Multiplier,
Traffic Light Controller,
Universal_Shift_Register,
BCD Adder,
Dual Address RAM and
Dual Address ROM
I2C and SPI Protocols
I2C Protocol
SPI Protocol
SPI_Master
SPI_Loopback
IEEE 754 Division
IEEE 754 Addition Subtraction
IEEE 754 Multiplication
CRC Coding
CRC_16_parallel
CRC_16_serial
CRC_32_parallel
CRC_32_serial
BCD Adder
Dual Address ROM
Dual Address RAM
Restoring and Non Restoring Division
Universal Shift Register
Barrel Shifter 8bit
Booth Multiplier
32 Bit Adder
Mealy State Machine for sequence detection
Moore State Machine for sequence detection
Array Multiplier
Carry Skip Adder
Carry Select Adder
Carry Look Ahead Adder
Carry Save Adder
Complex Multiplier
Logarithm Implementation
Traffic_Light_Controller
Shift and Add Binary Multiplier
Sequential Multiplier
Fixed Point Adder
Fixed Point Subtractor
Fixed Point Multiplier
Fixed Point Divider
Fraction_Multiplier
FIFO
LFSR and CFSR
LFSR
CFSR
Modified Booth Multiplication
Pipelined Multiplier
High Radix Multiplication
aieask/32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
Verilog