aignacio

ahb_lite_bus

AHB Bus lite v3.0

axi_dma

General Purpose AXI Direct Memory Access

cocotbext-ahb

Cocotb AHB Extension - AHB VIP

cocotbext-waves

Generate wavedrom figures out of design signals

digital_design_library

List of several designs I have been working through the years to avoid re-designing it again

iir_filter

IIR Lowpass Filter

mpsoc_example

nox

RISC-V Nox core

ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

riscv_verilator_model

RISCV model for Verilator/FPGA targets

aignacio/ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

aignacio/nox

RISC-V Nox core

aignacio/axi_dma

General Purpose AXI Direct Memory Access

aignacio/cocotbext-ahb

Cocotb AHB Extension - AHB VIP

aignacio/digital_design_library

List of several designs I have been working through the years to avoid re-designing it again

aignacio/nox_freertos

aignacio/soc_components

aignacio/cdc_components

Collection of different designs for clock domain crossing

aignacio/skid_buffer

aignacio/bus_arch_sv_pkg

AMBA SystemVerilog structs

aignacio/cache_performance_model

Simple cache model to evaluate performance through different topologies

aignacio/cocotbext-waves

Generate wavedrom figures out of design signals

aignacio/ethernet_axi

AXI wrapper around Ethernet module

aignacio/riscv-arch-test-nox

aignacio/riscv-formal

RISC-V Formal Verification Framework

aignacio/small_riscv_qemu_program

aignacio/axi_register_slice

AXI Register Slice used to break timing path in AXI bus

aignacio/cocotb_design_playground

Template repository for Cocotb RTL development

aignacio/DELETE_ME

aignacio/docker_images

Github Actions Container for RTL development

aignacio/ipsocgen_template

aignacio/learn

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

aignacio/openmp_eval_arm

aignacio/pcie_example

aignacio/pp-sp-reference-design

aignacio/rr_arbiter

aignacio/todeletelater

aignacio/verilog-axi

Verilog AXI components for FPGA implementation

aignacio/verilog_systemverilog.vim

Verilog/SystemVerilog Syntax and Omni-completion

aignacio/vim-header

Easily adds brief author info and license headers