aimilefth's Stars
aimilefth/TF2AIF
spcl/hls_tutorial_examples
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
Blaok/soda
Stencil with Optimized Dataflow Architecture
UCLA-VAST/tapa
TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators.