airhdl

Web-based VHDL/SystemVerilog AXI4 register generator for FPGA and ASIC projects.

Germany

Pinned Repositories

.github
0 1 00
lfsr-example
A PN9 sequence checker for the AD9645 analog-to-digital converter
Language:VHDL2 1 02
osvvm-demo
A project demonstrating how to use the OSVVM library and its Axi4LiteManager verification component to simulate an airhdl register bank.
Language:VHDL3 1 00
scripts
A collection of airhdl-related scripts
Language:Python2 1 10
spi-to-axi-bridge
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
Language:VHDL42 3 210

airhdl's Repositories

airhdl/spi-to-axi-bridge
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
Language:VHDL42 3 210
airhdl/osvvm-demo
A project demonstrating how to use the OSVVM library and its Axi4LiteManager verification component to simulate an airhdl register bank.
Language:VHDL3 1 00
airhdl/lfsr-example
A PN9 sequence checker for the AD9645 analog-to-digital converter
Language:VHDL2 1 02
airhdl/scripts
A collection of airhdl-related scripts
Language:Python2 1 10
airhdl/.github
0 1 00