Pinned Repositories
akankshac-073
Config files for my GitHub profile.
EEMCS-wip
Memory-Subsystem-Simulator
Memory Management Unit design consisting of a two-level hierarchical conventional TLB, L1 way-halting split cache, L2 cache, and main memory with pure paging as the memory management scheme, and page fault frequency as thrashing mechanism
MIPS-5-stage-pipelined-control-and-datapath
Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.
Preemptive-Test-Scheduling-in-Photonic-NoCs
mcqpa-sim-expts
This code simulates the exact schedulability test for EDF scheduling of semi-clairvoyant sporadic task systems with graceful degradation using the following two algorithms: (i) the previously proposed approach (listed as Algorithm 1 in the paper) and (ii) Mixed-Criticality Quick Processor-demand Analysis or MC-QPA (listed as Algorithm 2 in the paper).
akankshac-073's Repositories
akankshac-073/MIPS-5-stage-pipelined-control-and-datapath
Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.
akankshac-073/akankshac-073
Config files for my GitHub profile.
akankshac-073/EEMCS-wip
akankshac-073/Memory-Subsystem-Simulator
Memory Management Unit design consisting of a two-level hierarchical conventional TLB, L1 way-halting split cache, L2 cache, and main memory with pure paging as the memory management scheme, and page fault frequency as thrashing mechanism
akankshac-073/Preemptive-Test-Scheduling-in-Photonic-NoCs