Pinned Repositories
EasyCLA-code_only
Help_Wanted
Ideas that need engineering-power from the community for UHDM/Surelog/Related topics
simview
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
tsc
CHIPS Alliance Technical Steering Committee
UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
UHDM-integration-tests
verilator
yosys
Yosys Open SYnthesis Suite
yosys-uhdm-plugin-integration
SureLog - UHDM's Repositories
alainmarcel/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
alainmarcel/UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
alainmarcel/Help_Wanted
Ideas that need engineering-power from the community for UHDM/Surelog/Related topics
alainmarcel/yosys-uhdm-plugin-integration
alainmarcel/antlr4
ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.
alainmarcel/EasyCLA-code_only
alainmarcel/simview
alainmarcel/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
alainmarcel/tsc
CHIPS Alliance Technical Steering Committee
alainmarcel/UHDM-integration-tests
alainmarcel/verilator
alainmarcel/yosys
Yosys Open SYnthesis Suite