Question about the project coding style

[danieldanino17]

I'm trying to get better at verilog and i saw the project coding style and i get a little confused.
The FSMs are in the Mealy method but outputs updated according to clock. why to do so? why not to use the Moore method?
for example in the ip_eth_rx.v:

Here been created 2 registers: m_ip_hdr_valid_reg, m_ip_hdr_valid_next.
there is combinational always block that determines the value of m_ip_hdr_valid_next and there is clocked always block that assign m_ip_hdr_valid_next to m_ip_hdr_valid_reg:

And in the end there is an assign of m_ip_hdr_valid_reg to the output m_ip_hdr_valid:

Why to do this? why not to use one clocked always block and there you will control the FSM and the outputs? either way the outputs are clocked out.

I ask this only for self improvement and to get better understanding.