alexforencich/verilog-uart

Issues

• Is there any possibility that the reception module (uart_rx) is not working?

  #11 opened 10 months ago by AlexPop09
  1

• Hello, what's the difference between ready and busy in practice(usart_tx.rbl)

  #10 opened a year ago by jinbangju
  2

• AttributeError: 'HierarchyObject' object has no attribute '_entity'

  #9 opened 2 years ago by dattran96
  2

• Can I break the max speed limited by clk frequency?

  #6 opened 3 years ago by rliangcn
  2

• No CDC synchronizers at the RX input

  #8 opened 3 years ago by OVGN
  0

• cnt bits in uart_tx.v and uart_rx.v

  #7 opened 3 years ago by makararasi
  0

• create IP from verilog in vivado

  #4 opened 7 years ago by mhanuel26
  4

• max bir rate?

  #3 opened 8 years ago by Washix
  3

• Could you explain why the prescale should be set to Fclk / (baud * 8) according to verilog code?

  #2 opened 8 years ago by wuzh07
  1

• Testing the uart rx and tx using PuttY

  #1 opened 8 years ago by 108anup
  1