/UART

UART Transmitter & Receiver Using Verilog

Primary LanguageVerilog

UART

Implementaion of UART Transmitter & Receiver Using Verilog

Transmitter Architecture

Architecture (1)

Transmitter Testbench Simulation

top_module

Transmitter Features

  • 4 Baud Rates (2400, 4800, 9600, 19200) bit/second
  • 4 different parity options (no parity, odd parity, even parity, parallel odd parity)
  • Two modes for data (7 bits with 2 stop bits, 8 bits with 1 stop bit)

Receiver Architecture

uartReciver

Receiver FSM

  • using oversamplig to generate 16 tick for each bit.
  • when the state reach tick 8 (in the middle of bit time period) we capture the bit and save it in internal register.

fsm

Receiver Testbench Simulation

topModule

Reciver Features

  • 4 Baud Rates (2400, 4800, 9600, 19200) bit/second
  • Detecting errors using odd/parity checking