amal-khailtash

amal-khailtash's Stars

• deepseek-ai/DeepSeek-V3

  Language:Python92.8k72346915.1k

• isocpp/CppCoreGuidelines

  The C++ Core Guidelines are a set of tried-and-true guidelines, rules, and best practices about coding in C++

  Language:CSS43.4k2k1.2k5.5k

• pyper-dev/pyper

  Concurrent Python made simple

  Language:Python1.2k2723

• open-logic/open-logic

  Open Logic FPGA Standard Library

  Language:VHDL549223057

• b3b00/csly

  a C# embeddable lexer and parser generator (.Net core)

  Language:C#3861115434

• yuri-panchul/basics-graphics-music

  FPGA exercise for beginners

  Language:Verilog10213297

• ZipCPU/wbscope

  A wishbone controlled scope for FPGA's

  Language:Verilog77916

• jiacaiyuan/uvm-generator

  UVM Auto Generate ; Verify Project Build; Verilog Instance

  Language:Python34207

• TripRichert/viv-prj-gen

  tcl scripts used to build or generate vivado projects automatically

  Language:CMake29347

• gowinsemi/USB2I2S

  Language:GLSL23205

• yansyaf/cmake-verilog-vhdl-fpga-template

  CMake template for Verilog and VHDL project and Altera/Xilinx FPGA target

  Language:CMake2110010

• jol-jol/pymatlabparser

  A Matlab/Octave parser implemented in Python, using the Lex-Yacc framework.

  Language:Python18125

• eml-eda/messy

  Messy is an open-source framework that integrates a RISC-V ISS with SystemC-AMS

  Language:Python173202

• HEP-SoC/SoCMake

  CMake based hardware build system

  Language:CMake161442

• ImranR98/Wealthsimpleton

  A Python script that scrapes your Wealthsimple activity history and saves the data in a JSON file.

  Language:Python16204

• luzhixing12345/syntaxlight

  基于 BNF 的语法高亮

  Language:Python14224

• realistschuckle/pyvisitor

  An implementation of the visitor pattern for Python.

  Language:Python14206

• gboudreau/ws-api-python

  This library allows you to access your own account using the Wealthsimple (GraphQL) API using Python.

  Language:Python1223

• Luke7412/IpLibrary

  Library containing various VHDL IPs

  Language:SystemVerilog7002

• bit-zone/SystemVerilog-Specific-Parser

  This is a specific parser to SystemVerilog used for Hardware Constraints Solver

  Language:Python6101

• srjilarious/fpga_start

  Language:C++5121

• domino644/sly-compiler

  Compiler made in SLY for Theory of Compiling AGH course

  Language:Python2101

• halotukozak/CompilationTheory

  Language:Python20

• HEP-SoC/svuvm-socmake

  SystemVerilog UVM SoCMake package

  Language:CMake1

• kraj/rwmem

  A small tool to read & write device registers

  Language:C++120

• mballance/ipxact

  IP-XACT schema

  Language:Shell120

• PaulMSV/ipxact2sv

  Генерация SystemVerilog кода и документации для регистровой карты из IP-XACT XML описания

  Language:Python11

• RHamalainen/ipxact-parser

  1100

• Risto97/svuvm-socmake

  SystemVerilog UVM SoCMake package

  Language:CMake11

• vladyslav-dubina/SV2Aplan

  Translator from the System verilog language to the AVM algebraic model

  Language:Python1