/zedboard-base

Base project for the ZedBoard

Primary LanguageTcl

zedboard-base

Base project for the ZedBoard

Requirements

This project is designed for Vivado 2019.2. If you are using an older version of Vivado, then you MUST use an older version of this repository. Refer to the list of commits to find links to the older versions of this repository.

  • ISE Design Suite 14.7 or Vivado 2019.2
  • ZedBoard

Description

This project is a base system for the ZedBoard. The design contains only the Zynq PS and is designed for and tested on the ZedBoard.

A tutorial for recreating this project in the Vivado GUI can be found here:

http://www.fpgadeveloper.com/2014/07/creating-a-base-system-for-the-zynq-in-vivado.html

Build instructions

To use the sources in this repository, please follow these steps:

  1. Download the repo as a zip file and extract the files to a directory on your hard drive --OR-- Git users: clone the repo to your hard drive
  2. Open Windows Explorer, browse to the repo files on your hard drive.
  3. In the Vivado directory, you will find multiple batch files (*.bat). Double click build.bat. This will generate a Vivado project for the ZedBoard.
  4. Run Vivado and open the project that was just created.
  5. Click Generate bitstream.
  6. When the bitstream is successfully generated, select File->Export->Export Hardware. In the window that opens, tick "Include bitstream" and "Local to project".
  7. Select the Launch SDK option from the File menu in Vivado.
  8. Generate a hello world application in SDK.
  9. Connect and power up the hardware.
  10. Open a Putty terminal to view the UART output.
  11. In the SDK, select Xilinx Tools->Program FPGA.
  12. Right-click on the application and select Run As->Launch on Hardware (System Debugger)

Troubleshooting

Check the following if the project fails to build or generate a bitstream:

1. Are you using the correct version of Vivado for this version of the repository?

Check the version specified in the Requirements section of this readme file. Note that this project is regularly maintained to the latest version of Vivado and you may have to refer to an earlier commit of this repo if you are using an older version of Vivado.

2. Did you follow the Build instructions in this readme file?

All the projects in the repo are built, synthesised and implemented to a bitstream before being committed, so if you follow the instructions, there should not be any build issues.

3. Did you copy/clone the repo into a short directory structure?

Vivado doesn't cope well with long directory structures, so copy/clone the repo into a short directory structure such as C:\projects\. When working in long directory structures, you can get errors relating to missing files, particularly files that are normally generated by Vivado (FIFOs, etc).

License

Feel free to modify the project or use it as a base for your application.

Fork and share

If you port this project to another hardware platform, please send me the code or push it onto GitHub and send me the link so I can post it on my website. The more people that benefit, the better.

About us

This project was developed by Opsero Inc., a tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. Follow our blog, FPGA Developer, for news, tutorials and updates on the awesome projects we work on.