2020.1 Vitis™ Application Acceleration Development Flow Tutorials

Getting Started

Tutorial	Kernel	Description
Getting Started with RTL Kernels	RTL	This tutorial demonstrates how to use the Vitis core development kit to program an RTL kernel into an FPGA and build a Hardware Emulation using a common development flow.
Vitis HLS Analysis and Optimization	C	This tutorial demonstrates how you can use the Vitis HLS tool GUI to build, analyze, and optimize a hardware kernel.
Mixing C and RTL	C and RTL	This tutorial demonstrates working with an application containing RTL and OpenCL™ kernels to familiarize yourself with the Vitis core development kit flow, along with various design analysis features.
Using Multiple Compute Units	C and RTL	This tutorial demonstrates the flexible kernel linking process to increase the number of kernel instances on an FPGA, which improves the parallelism in a combined host-kernel system.
Host Code Optimization	C and RTL	This tutorial demonstrates applying host code optimization techniques to your design.
Using Multiple DDR Banks	C and RTL	This tutorial demonstrates how using multiple DDRs can improve data transfer between kernels and global memory.

Tutorial	Kernel	Description
Controlling Vivado Implementation	RTL	This tutorial demonstrates how you can control the Vivado® tools flow when implementing your project.