Kernel 6.9 released
Closed this issue · 4 comments
tw-atroehrsm commented
Hello,
question. Does Kernel 6.9 include the necessary patches (IOMMU SVA) or does it still require a custom kernel?
Thx
garloff commented
We'll need to cherry pick (in reverse order) a subset from the following list I guess ...
b194fc01fbaf5 platform/x86/amd/pmc: Add 10ms delay to 2nd s0i3 cycle for all APUs
1cf1c512d240d Add compilation recipe for AMD IOMMU SVA branches
39ecf66190804 Better describe branches for AMD IOMMU SVA
591b43ada1659 Add AMD-specific README about RyzenAI an IOMMU SVA
759eb0ce6369d iommu/amd: Add SVA domain support
811fefdb25a1f iommu: Add ops->domain_alloc_sva()
0aa515afdb098 iommu/amd: Initial SVA support for AMD IOMMU
95d5d54b96628 iommu/amd: Add support for enable/disable IOPF
5ec1dfbdcf9f6 iommu/amd: Add IO page fault notifier handler
5a28ef6a108f8 iommu/amd: Add support for page response
fa8b5564e1a6b iommu/amd: Define per-IOMMU iopf_queue
d6650f92fee8f iommu/amd: Enable PCI features based on attached domain capability
4008d455c1a61 iommu/amd: Setup GCR3 table in advance if domain is SVA capable
82bc8f69d14c8 iommu/amd: Introduce iommu_dev_data.max_pasids
4d12b7d853f02 iommu/amd: Fix PPR interrupt processing logic
af2a86616ca3b iommu/amd: Move PPR-related functions into ppr.c
f648e97453492 iommu/amd: Add support for enabling/disabling IOMMU features
da271b4b64ad0 iommu/amd: Introduce per device DTE update function
b213215e9ea7d iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_pasid_supported()
a1130eba6fb6b PART4: SVA support (SVA + IOPF)
6d613f9ffb3c7 iommu/dma: Document min_align_mask assumption
ea3ffc00f9899 iommu: re-use local fwnode variable in iommu_ops_from_fwnode()
87387617a2867 iommu: constify fwnode in iommu_ops_from_fwnode()
69678527c2824 iommu: constify of_phandle_args in xlate
59eab561a1b42 iommu: constify pointer to bus_type
f0b80b686e9ab iommu: Make iommu_report_device_fault() return void
27dd47f202aae iommu: Make iopf_group_response() return void
2c7f972f959bb iommu: Track iopf group instead of last fault
90dfd8d99628c iommu: Improve iopf_queue_remove_device()
2c730b58ab937 iommu: Use refcount for fault data access
34e0559bf9e77 iommu: Refine locking for per-device fault data management
0ce696f91a5f5 iommu: Separate SVA and IOPF
9a88a21300f5d iommu: Make iommu_queue_iopf() more generic
ae45ccdf0a5b0 iommu: Prepare for separating SVA and IOPF
e15e6051c1057 iommu: Merge iommu_fault_event and iopf_fault
55e171c62cd6d iommu: Remove iommu_[un]register_device_fault_handler()
a765125103aa2 iommu: Merge iopf_device_param into iommu_fault_param
ce65c1fcbb89f iommu: Cleanup iopf data structure definitions
2bf610472277d iommu: Remove unrecoverable fault data
52494c29e6e16 iommu/arm-smmu-v3: Remove unrecoverable faults reporting
c50ef18dd5203 iommu: Move iommu fault data to linux/iommu.h
6fc11da880591 iommu/iova: use named kmem_cache for iova magazines
38be7da505588 iommu/iova: Reorganise some code
4971e0027f210 iommu/iova: Tidy up iova_cache_get() failure
4f08455c91bbd iommu/amd: Fix sleeping in atomic context
f616d3dfdeb54 iommu/amd: Introduce per-device domain ID to fix potential TLB aliasing issue
b380cd7b7f043 iommu/amd: Remove unused GCR3 table parameters from struct protection_domain
8140e2cce018a iommu/amd: Rearrange device flush code
06ec65899a23f iommu/amd: Remove unused flush pasid functions
64e375a08f330 iommu/amd: Refactor GCR3 table helper functions
c35954cd0879b iommu/amd: Refactor protection_domain helper functions
a133b92ead7ca iommu/amd: Refactor attaching / detaching device functions
6986d0f234f58 iommu/amd: Refactor helper function for setting / clearing GCR3
4fd7f0c29d900 iommu: Introduce iommu_group_mutex_assert()
c484bd0eb4eae iommu/amd: Rearrange GCR3 table setup code
8fedb283925b0 iommu/amd: Add support for device based TLB invalidation
c49986de9d79c iommu/amd: Use protection_domain.flags to check page table mode
bca5cf99d1f9c iommu/amd: Introduce per-device GCR3 table
fe211f0d1e90a iommu/amd: Introduce struct protection_domain.pd_mode
61c1f4042b68c iommu/amd: Introduce get_amd_iommu_from_dev()
34efcfdc20eb2 iommu/amd: Enable Guest Translation before registering devices
c54a5eb52308b iommu/amd: Pass struct iommu_dev_data to set_dte_entry()
4521a75fbc935 iommu/amd: Remove EXPORT_SYMBOL for perf counter related functions
48ad6c5eddd21 iommu/amd: Remove redundant error check in amd_iommu_probe_device()
64e0053098891 iommu/amd: Remove duplicate function declarations from amd_iommu.h
22dff8305b8a6 iommu/amd: Remove unused APERTURE_* macros
4a333c7018e9d iommu/amd: Remove unused IOVA_* macro
4b96670850196 iommu/amd: Remove unused PPR_* macros
(I'll write a followup as soon as I have a working set.)
nstiurca commented
I've been trying to track when this is mainlined as well, and from what I can tell 6.10 is the most likely version to contain all the necessary patches. In fact I think last week's 6.10-rc1 (probably) has all these patches.
Part 4 (of 4) of the patch series (ie, the patches listed above) was applied on Apr 18 and got pulled into Linus's tree about 2 weeks ago.
maxzhen commented
Yes, 6.10 should have all the patches we need. We're internally testing 6.10. We'll update this repo when we complete the test.
garloff commented
Cherry-picking
b194fc01fbaf5 platform/x86/amd/pmc: Add 10ms delay to 2nd s0i3 cycle for all APUs
1cf1c512d240d Add compilation recipe for AMD IOMMU SVA branches
39ecf66190804 Better describe branches for AMD IOMMU SVA
591b43ada1659 Add AMD-specific README about RyzenAI an IOMMU SVA
759eb0ce6369d iommu/amd: Add SVA domain support
811fefdb25a1f iommu: Add ops->domain_alloc_sva()
0aa515afdb098 iommu/amd: Initial SVA support for AMD IOMMU
95d5d54b96628 iommu/amd: Add support for enable/disable IOPF
5ec1dfbdcf9f6 iommu/amd: Add IO page fault notifier handler
5a28ef6a108f8 iommu/amd: Add support for page response
fa8b5564e1a6b iommu/amd: Define per-IOMMU iopf_queue
d6650f92fee8f iommu/amd: Enable PCI features based on attached domain capability
4008d455c1a61 iommu/amd: Setup GCR3 table in advance if domain is SVA capable
82bc8f69d14c8 iommu/amd: Introduce iommu_dev_data.max_pasids
4d12b7d853f02 iommu/amd: Fix PPR interrupt processing logic
af2a86616ca3b iommu/amd: Move PPR-related functions into ppr.c
f648e97453492 iommu/amd: Add support for enabling/disabling IOMMU features
da271b4b64ad0 iommu/amd: Introduce per device DTE update function
b213215e9ea7d iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_pasid_supported()
a1130eba6fb6b PART4: SVA support (SVA + IOPF)
and commenting out the line 196 in drivers/iommu/amd/ppr.c:
//if (!amd_iommu_snp_en)
raw[0] = raw[1] = 0UL;to make it compile was successful for me.
garloff@framekurt(//):~ [0]$ uname -a
Linux framekurt 6.9.3-sva4-KG+ #2 SMP PREEMPT_DYNAMIC Sat Jun 1 09:02:58 UTC 2024 x86_64 x86_64 x86_64 GNU/Linux
garloff@framekurt(//):~ [0]$ dmesg | grep -C1 amdxdna
[ 3.798179] ccp 0000:c1:00.2: psp enabled
[ 3.800229] amdxdna: loading out-of-tree module taints kernel.
[ 3.802884] amd-tee driver initialization successful
[ 3.805391] hid-sensor-hub 0018:32AC:001B.0002: hidraw1: I2C HID v1.00 Device [FRMW0005:00 32AC:001B] on i2c-FRMW0005:00
[ 3.847207] amdxdna 0000:c2:00.1: (Develop) IOMMU mode is 0
[ 3.882695] mc: Linux media interface: v0.10
[ 3.885573] amdxdna 0000:c2:00.1: set mpnpu_clock = 600 mhz
[ 3.886475] cros_ec_lpcs cros_ec_lpcs.0: loaded with quirks 00000001
[ 3.896724] cros_ec_lpcs cros_ec_lpcs.0: Chrome EC device registered
[ 3.904573] amdxdna 0000:c2:00.1: set npu_hclock = 1024 mhz
[ 3.907055] RAPL PMU: API unit is 2^-32 Joules, 1 fixed counters, 163840 ms ovfl timer
--
[ 3.918260] amd-pmf AMDI0102:00: registered PMF device successfully
[ 3.945704] [drm] Initialized amdxdna_accel_driver 1.0.0 20240124 for 0000:c2:00.1 on minor 0
[ 3.953256] Adding 8388604k swap on /dev/nvme0n1p3. Priority:41 extents:1 across:8388604k SSIf we can work with an unpatched upstream 6.10 kernel, that would of course be better.