Issues
- 1
- 1
variable time between verilator ticks
#33 opened by drom - 1
BigInt for signals longer then 32bit
#37 opened by drom - 0
method to finish simulation
#38 opened by drom - 0
check names, direction, width at compile time
#36 opened by drom - 0
make template requirable
#35 opened by drom - 0
DuH support
#34 opened by drom - 1
Add forks
#17 opened by ameetgohil - 0
Add PublishPort
#29 opened by ameetgohil - 0
Add TxnFifo
#30 opened by ameetgohil - 1
Add regression test tutorial (mocha)
#13 opened by ameetgohil - 1
Update docs for phases
#28 opened by ameetgohil - 1
Add simulation phases
#12 opened by ameetgohil - 1
Add Edge, Edges
#27 opened by ameetgohil - 1
add runUntil function
#25 opened by ameetgohil - 1
add a finish option in sim.run
#26 opened by ameetgohil - 1
Fix elastic ready driver - for TARGET
#23 opened by ameetgohil - 1
Add time property in Sim.js
#24 opened by ameetgohil - 1
- 1
fix sc_time - needed for assertions
#21 opened by ameetgohil - 1
add a way to add verilator params and defines
#15 opened by ameetgohil - 1
Switch to N-API property descriptors
#20 opened by ameetgohil - 1
Multiple clock generation
#18 opened by ameetgohil - 1
Add Tick - move simulation forward 1 step
#19 opened by ameetgohil - 6
Read Verilog pinlist
#9 opened by drom - 0
reorg scripts out of root directory
#16 opened by ameetgohil - 1
- 0
Multithreading support
#10 opened by ameetgohil - 1
Add option to generate fst waveforms
#14 opened by ameetgohil - 1
- 1
- 4
fatal error: napi.h: No such file or directory
#3 opened by drom - 7
node: symbol lookup error
#5 opened by drom - 2
missing ../obj_dir/verilator_global_libs.a
#2 opened by drom - 1
Switch to C
#1 opened by drom