These are exercises for digital system design course. All of them are in VHDL.
2 bit register with enable.
Array Multiplier with test bench.
Universal Counter with test bench.
ops:
- 0: np op
- 1: dout <= din
- 2: count up
- 3: count down
- 4: logical right shift
- 5: logical left shift
- 6: circular right shift
- 7: circular left shift
A 32-bit ALU using bit slice 1-bit ALUs. More info here.
data-path for a simple cpu is implemented. info about instructions are here.
full uart with t0 standard. More info here.