A course project of Computer Architecture. To implement a pipeline CPU
- using Chisel and Scala
- modified by riscv-sodor
- using MIPS instruction set (instead of RISC-V instruction set)
- Cache and Memory parts modified by Tao Jin's code
- verified at Digilent NEXYS 3
All instructions in the memory, and it executes step-by-step through buttons and switchs at NEXYS.
- riscv-sodor: https://github.com/ucb-bar/riscv-sodor
- UC Berkeley CS152: http://www-inst.eecs.berkeley.edu/~cs152/sp16/
- Modified version by Tao Jin: https://github.com/tao-j/Duo-RISC