This repository contains a dataset of maximum period nonlinear feedback shift registers (NLFSRs) as well as the source code of the FPGA accelerator that has been used to build it. More about the accelerator, search method, and results can be found in the paper "An FPGA Accelerated Search Method for Maximum Period NLFSRs" presented at WAIFI 2024.
The dataset is in JSON format and available in the file dataset/nlfsr_dataset.json. The dataset is indexed by the bit-width of the shift registers, and the form of the feedback function for the NLFSRs. For the form, we use a shorthand notation representing the number of terms in ascending order. For example "7,0,1" means 7 linear terms and one cubic term. For each combination of shift register width and form, the dataset contains a list of feedback functions that correspond to maximum period NLFSRs. The format we use to represent a feedback function is a list of terms. Each term is in turn represented as a list of the bit indexes that are multiplied together to form the term. For example [[0], [1], [4], [3, 7]] represents the feedback function x_0 + x_1 + x_4 + x_3 * x_7.
The file dataset/example.py contains some example code that reads from the dataset. The file software/nlfsr_utils.py contains various functions that are useful when interacting with the dataset.
The code for the FPGA accelerator is written in Verilog and can be found in the HDL folder. This project uses cocotb testbenches written in Python together with pytest for verification. The testbenches are located in folders named verification in the various module folders. Running testbenches can be done with e.g pytest -s --tb=no --full in one of the verification folders, the option --full is for running all tests. Other available options are described in conftest.py.
A Vivado project targeting the Genesys 2 board can be generated by running vivado -mode batch -source generate_project.tcl in the HDL folder. This project can easily be used with other boards using Xilinx 7-series or UltraScale FPGAs, by replacing the genesys_top_wrapper.v file with your own wrapper file. This project should also be adaptable to non-Xilinx FPGAs, however, that will require a new FIFO implementation.