Pinned Repositories
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
basic_verilog
Must-have verilog systemverilog modules
NutShell
RISC-V SoC designed by students in UCAS
riscv-linux
RISC-V Linux Port
rocket-chip
Rocket Chip Generator
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
XJTU-Tripler
This repository is the backup of XJTU-Tripler project, participating dac19 system design contest
ZJU-nCov-Hitcarder-Sample
Sample of https://github.com/Long0x0/ZJU-nCov-Hitcarder.
andy89926's Repositories
andy89926/AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
andy89926/basic_verilog
Must-have verilog systemverilog modules
andy89926/NutShell
RISC-V SoC designed by students in UCAS
andy89926/riscv-linux
RISC-V Linux Port
andy89926/rocket-chip
Rocket Chip Generator
andy89926/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
andy89926/XJTU-Tripler
This repository is the backup of XJTU-Tripler project, participating dac19 system design contest
andy89926/ZJU-nCov-Hitcarder-Sample
Sample of https://github.com/Long0x0/ZJU-nCov-Hitcarder.