andydaydayup

Pinned Repositories

andydaydayup
Config files for my GitHub profile.
00
FPGA_ADC
An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
Language:VHDL00
jTDC
FPGA based 30ps RMS TDCs
Language:VHDL00
tdc
A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.
Language:VHDL10
tdc-core
A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
Language:VHDL00
TDC-Vernier-Method
Time-to-Digital Converter based on Vernier method with two ring oscillators
Language:VHDL00

andydaydayup's Repositories

andydaydayup/tdc
A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.
Language:VHDL10
andydaydayup/andydaydayup
Config files for my GitHub profile.
00
andydaydayup/FPGA_ADC
An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
Language:VHDL00
andydaydayup/jTDC
FPGA based 30ps RMS TDCs
Language:VHDL00
andydaydayup/tdc-core
A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
Language:VHDL00
andydaydayup/TDC-Vernier-Method
Time-to-Digital Converter based on Vernier method with two ring oscillators
Language:VHDL00