anjianfeng
Associate professor in Northwestern Polytechnical University of China.
Northwestern Polytechnical UniversityXi'an City, Shaanxi Province
Pinned Repositories
anjianfeng.github.io
chiffreExample
ChiselMIPS
a MIPS example written by Chisel.
LogisimMIPS
Logisim MIPS examples.
noc
For NOC lesson.
processor
For computer organization and computer architecuture lesson.
uart
A general UART design for FPGA debugging.
VerilogMIPS-multicycle-uart
A multicycle MIPS processor for teaching.
VerilogMIPS-singlecycle
Verilog MIPS of Single cycle for teaching.
ercesiMIPS
This repo has been put together to demonstrate a number of simple MIPS Processors written in Chisel.
anjianfeng's Repositories
anjianfeng/noc
For NOC lesson.
anjianfeng/LogisimMIPS
Logisim MIPS examples.
anjianfeng/VerilogMIPS-multicycle-uart
A multicycle MIPS processor for teaching.
anjianfeng/anjianfeng.github.io
anjianfeng/chiffreExample
anjianfeng/ChiselMIPS
a MIPS example written by Chisel.
anjianfeng/processor
For computer organization and computer architecuture lesson.
anjianfeng/uart
A general UART design for FPGA debugging.
anjianfeng/VerilogMIPS-singlecycle
Verilog MIPS of Single cycle for teaching.