anotherlin/z80emu

2 instructions in one step

Closed this issue · 3 comments

akirender commented

First, thanks for this project, it helps me a lot ^^ I'm trying to create a java z80 just for fun and I'm using z80emu step by step as a reference to correct my emulator and it's a huuuuuuge help to be able to step by step zexdoc and zexall !

But while running zexdoc at step 3115 we have a DI instruction:

1d2e f3             DI
1d2f ed 73 8d 1d    LD (1d8d),SP
1d33 31 05 01       LD SP,0105

step=3115
a=cd f=8b b=00 c=09 d=02 e=03 h=00 l=2c i=00 r=0d ixl=00 ixh=00 iyl=00 iyh=00 
sp=c8f0 pc=1d2e iff1=0 iff2=0 m=0 
mem=f3 ed 73 8d 1d 
stack=2c 00 03 02 09
(hl)=00 (de)=3c (ix)=d3 00 00 00 00 (iy)=d3 00 00 00 00

And at next step, the status is:

step=3116 
a=cd f=8b b=00 c=09 d=02 e=03 h=00 l=2c i=00 r=10 ixl=00 ixh=00 iyl=00 iyh=00 
sp=c8f0 pc=1d33 iff1=0 iff2=0 m=0 
mem=31 05 01 fd e1
stack=2c 00 03 02 09 
(hl)=00 (de)=3c (ix)=d3 00 00 00 00 (iy)=d3 00 00 00 00

PC has moved to address 1d33 instead of 1d2f and R has moved from 0d to 10.
It seems that 2 instructions has been executed instead of just DI.

There is not wrong z80 implementation, but 2 steps have been executed instead of one, is this a design choice ?

Thanks

akirender commented

I've found my answer in DI implementation comment in the code:

                                /* No interrupt can be accepted right after
                                 * a DI or EI instruction on an actual Z80 
                                 * processor. By adding 4 cycles to 
                                 * number_cycles, at least one more 
                                 * instruction will be executed. However, this
                                 * will fail if the next instruction has
                                 * multiple 0xdd or 0xfd prefixes and
                                 * Z80_PREFIX_FAILSAFE is defined, but that
                                 * is an unlikely pathological case.
                                 */

I guess that's a design choice to allow interruptions only between two calls to Z80Emulate and forcing next instruction to be executed avoid allowing simulating an interruption between them.

akirender commented

I've found my answer in DI implementation comment in the code:

                                /* No interrupt can be accepted right after
                                 * a DI or EI instruction on an actual Z80 
                                 * processor. By adding 4 cycles to 
                                 * number_cycles, at least one more 
                                 * instruction will be executed. However, this
                                 * will fail if the next instruction has
                                 * multiple 0xdd or 0xfd prefixes and
                                 * Z80_PREFIX_FAILSAFE is defined, but that
                                 * is an unlikely pathological case.
                                 */

I guess that's a design choice to allow interruptions only between two calls to Z80Emulate and forcing next instruction to be executed avoid allowing simulating an interruption between them.

anotherlin commented
  • 👍1