anthonywang376

anthonywang376's Stars

• cjhonlyone/NandFlashController

  AXI Interface Nand Flash Controller (Sync mode)

  Language:Verilog8438

• Qertile/NAND-Flash-Controller

  Language:Verilog1

• thesourcerer8/nand_controller

  NAND Controller, targeting ONFI and non-compliant flash

  Language:SystemVerilog4

• m-liu/NandController

  Language:Verilog51

• raiyyanfaisal09/RTL_NAND_Flash_controller

  Language:Verilog168

• gyd111/NAND-Flash-controller

  MT29F128G based NAND flash controller

  Language:Verilog9

• boaaaang/CNN-Implementation-in-Verilog

  Convolutional Neural Network RTL-level Design

  Language:Verilog4016

• sedoy-jango-2/MobileNet_FPGA_MNIST_letters

  Language:Verilog6

• ZFTurbo/MobileNet-in-FPGA

  Generator of verilog description for FPGA MobileNet implementation

  Language:Verilog15231

• kevin199907/AOC

  NCKU AOC course 2024

  Language:Jupyter Notebook4

• suchuankai/CNN-hw-accelerator

  CNN hardware accelerator to accelerate quantized LeNet-5 model

  Language:Verilog234

• Jorgeortiz97/lenet5

  Language:Verilog22

• wcy777/Convolution_Accelerator_for_VGG-16

  Language:Verilog1

• abob208/Convolution-Accelerator-for-VGG-16

  Language:Verilog1

• proy10/RepVGG_acc

  Language:Verilog1

• SilentEllise/SoC-VGGrep

  Language:Verilog1

• romulus0914/CNN_VGG19_verilog

  Convolution Neural Network of vgg19 model in verilog

  Language:Verilog4514

• PhanQuocLinh/Project_VGG16

  Language:Verilog2

• WenqiJiang/VGG16_FPGA_Accelerator

  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 16 (fp16).

  Language:C2910

• zhan6841/FPGA-Accelerator-for-AES-LeNet-VGG16

  FPGA/AES/LeNet/VGG16

  Language:Verilog9022

• ChrisZonghaoLi/cnn_conv_accelerator

  A Fix-pointed Rudimentary CNN Convolution Accelerator

  Language:Verilog133

• chenwei0129/Systolic_Array_Based_on_Matrix_Multiplication_for_CNN

  Language:Verilog7

• VincentWang1998/ai_on_chip_project1

  tpu-systolic-array-weight-stationary

  Language:Verilog203

• Spiritator/FPGA_LeNet5_ws_8x8

  FPGA implement of 8x8 weight stationary systolic array DNN accelerator

  Language:Verilog104

• LEAUQEAAN/e203_Four-stageToFive-stage

  e203_Four-stageToFive-stage

  Language:Verilog5

• mfkiwl/E203_dma

  9

• eda-lab/CNNAF-CNN-Accelerator_init

  CNN-Accelerator based on FPGA developed by verilog HDL.

  Language:Verilog456

• diaoenmao/FPGA-CNN

  FPGA implementation of Cellular Neural Network (CNN)

  Language:Verilog13682

• VGuoGavin/Hand-Writing-Digital-Recognization-Based-on-FPGA

  Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The SoC worked not bad in the end the success rate up to 90%。.

  Language:Verilog105

• huangxc6/E203_CNN_Genesys2

  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.

  Language:VHDL11