Building does not work with Python 3.11

[maxammann]

I get the following error from litex. It seems slightly werid because that is because a name is not passed to CSRStorage.

lxbuildenv: v2020.6.1.1 (run ./bitstream.py --lx-help for help)
fatal: destination path 'valentyusb' already exists and is not an empty directory.
INFO:SoC:        __   _ __      _  __
INFO:SoC:       / /  (_) /____ | |/_/
INFO:SoC:      / /__/ / __/ -_)>  <
INFO:SoC:     /____/_/\__/\__/_/|_|
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2023-10-15 17:07:45)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : ice40-up5k-uwg30.
INFO:SoC:System clock: 12.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
Traceback (most recent call last):
  File "/Users/pax/projects/fomu/fomu-keystroke-injector/hw/./bitstream.py", line 126, in <module>
    main()
  File "/Users/pax/projects/fomu/fomu-keystroke-injector/hw/./bitstream.py", line 72, in main
    soc = BaseSoC(bios_flash_offset=flash_offset_bios,
          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/Users/pax/projects/fomu/fomu-keystroke-injector/hw/deps/litex-boards/litex_boards/targets/kosagi_fomu.py", line 90, in __init__
    SoCCore.__init__(self, platform, sys_clk_freq,
  File "/Users/pax/projects/fomu/fomu-keystroke-injector/hw/deps/litex/litex/soc/integration/soc_core.py", line 183, in __init__
    self.add_controller("ctrl")
  File "/Users/pax/projects/fomu/fomu-keystroke-injector/hw/deps/litex/litex/soc/integration/soc.py", line 823, in add_controller
    setattr(self.submodules, name, SoCController(**kwargs))
                                   ^^^^^^^^^^^^^^^^^^^^^^^
  File "/Users/pax/projects/fomu/fomu-keystroke-injector/hw/deps/litex/litex/soc/integration/soc.py", line 672, in __init__
    self._reset = CSRStorage(fields=[
                  ^^^^^^^^^^^^^^^^^^^
  File "/Users/pax/projects/fomu/fomu-keystroke-injector/hw/deps/litex/litex/soc/interconnect/csr.py", line 383, in __init__
    _CompoundCSR.__init__(self, size, name)
  File "/Users/pax/projects/fomu/fomu-keystroke-injector/hw/deps/litex/litex/soc/interconnect/csr.py", line 131, in __init__
    _CSRBase.__init__(self, size, name)
  File "/Users/pax/projects/fomu/fomu-keystroke-injector/hw/deps/litex/litex/soc/interconnect/csr.py", line 50, in __init__
    raise ValueError("Cannot extract CSR name from code, need to specify.")
ValueError: Cannot extract CSR name from code, need to specify.

[maxammann]

Aaah it works with Python 3.8 :)