antoinemadec/vim-verilog-instance
verilog_instance.vim: create instantiation of ports from port declaration
PythonMIT
Issues
- 2
Keep comments
#3 opened by gogulfresh - 2
Add LICENSE file
#7 opened by toddky - 7
Support wire declaration
#4 opened by KyleJeong - 2
helptags error message
#5 opened by KyleJeong - 1
',' on last port
#2 opened by kiteloopdesign - 2
, after last port instance
#1 opened by gogulfresh