antonblanchard

@tenstorrent

Pinned Repositories

chiselwatt
A tiny POWER Open ISA soft processor written in Chisel
Language:Scala101 14 515
crc32-vpmsum
Accelerated CRC32 for POWER8 using vpmsum instructions
Language:C32 10 312
ghdl-yosys-blink
Blink an LED on an FPGA in VHDL using ghdl, yosys and nextpnr
Language:Makefile25 7 15
kexec-lite
Language:C617
microwatt
A tiny Open POWER ISA softcore written in VHDL 2008
Language:Verilog653 41 7198
microwatt-mpw1
The 64 bit OpenPOWER Microwatt core, MPW1 tape out
Language:Verilog174
microwatt-mpw5
The 64 bit OpenPOWER Microwatt core, MPW5 tape out
Language:Verilog5 2 00
qtrace-tools
Tools to read and write qtrace instruction traces
Language:C6 8 114
vlsiffra
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
Language:Python107 7 169
will-it-scale
Language:C66 12 534

antonblanchard's Repositories

antonblanchard/microwatt
A tiny Open POWER ISA softcore written in VHDL 2008
Language:Verilog653 41 7198
antonblanchard/vlsiffra
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
Language:Python107 7 169
antonblanchard/chiselwatt
A tiny POWER Open ISA soft processor written in Chisel
Language:Scala101 14 515
antonblanchard/will-it-scale
Language:C66 12 534
antonblanchard/qtrace-tools
Tools to read and write qtrace instruction traces
Language:C6 8 114
antonblanchard/microwatt-caravel
Language:Verilog4 3 02
antonblanchard/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
Language:Verilog4 3 01
antonblanchard/microwatt-mpw7
Language:Verilog3 3 1
antonblanchard/openlane
OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
Language:Verilog2 2 01
antonblanchard/caravel
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Language:Verilog1 2 0
antonblanchard/DFFRAM
Standard Cell Library based Memory Compiler using DFF cells
Language:Verilog1 2 0
antonblanchard/ghdl
VHDL 2008/93/87 simulator
Language:VHDL1 2 01
antonblanchard/linux
Linux kernel source tree
Language:C1 4 01
antonblanchard/OpenROAD-flow-scripts
Language:Verilog1 2 0
antonblanchard/skywater-pdk-libs-sky130_fd_sc_hd
Language:Verilog1 2 0
antonblanchard/verilator
Verilator open-source SystemVerilog simulator and lint system
Language:C++1 2 01
antonblanchard/ASAP7_for_KLayout
KLayout technology files for ASAP7 FinFET educational process
2 0
antonblanchard/bigspicy
Language:Python2 0
antonblanchard/caravel_mgmt_soc_litex
Language:Verilog2 0
antonblanchard/lz4
Extremely Fast Compression algorithm
Language:C1 0
antonblanchard/lzo
Unofficial mirror of LZO
Language:C1 0
antonblanchard/magic
Magic VLSI Layout Tool
Language:C2 01
antonblanchard/microwatt-gfmpw0
3 0
antonblanchard/microwatt-mpw8
3 0
antonblanchard/netgen
Netgen complete LVS tool for comparing SPICE or verilog netlists
Language:C2 0
antonblanchard/open_pdks
PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.
Language:Python2 01
antonblanchard/skywater-pdk-libs-sky130_fd_io
IO and periphery cells for SKY130 provided by SkyWater.
2 0
antonblanchard/smash
Smash - Compression Abstraction Library
Language:C++1 0
antonblanchard/yosys
Yosys Open SYnthesis Suite
Language:C++2 0
antonblanchard/zstd
Zstandard - Fast real-time compression algorithm
Language:C1 0