anupama-k's Stars
freeCodeCamp/freeCodeCamp
freeCodeCamp.org's open-source codebase and curriculum. Learn to code for free.
ziishaned/learn-regex
Learn regex the easy way
datasciencemasters/go
The Open Source Data Science Masters
dive-into-machine-learning/dive-into-machine-learning
Free ways to dive into machine learning with Python and Jupyter Notebook. Notebooks, courses, and other links. (First posted in 2016.)
thoughtbot/dotfiles
A set of vim, zsh, git, and tmux configuration files.
purcell/emacs.d
An Emacs configuration bundle with batteries included
redguardtoo/mastering-emacs-in-one-year-guide
Be great at emacs in one year
Fuco1/smartparens
Minor mode for Emacs that deals with parens pairs and tries to be smart about it.
trizen/youtube-viewer
Lightweight YouTube client for Linux
VerticalResearchGroup/miaow
An open source GPU based off of the AMD Southern Islands ISA.
mscoutermarsh/dotfiles
my Vim/Tmux config :muscle::zap:
zhemao/ez8
The Easy 8-bit Processor
NetFPGA/NetFPGA-public
NetFPGA public repository
pjcj/Devel--Cover
Code coverage metrics for Perl
SimpleCPU/SimpleCPU
An open source CPU design and verification platform for academia
soarpenguin/perl-scripts
useful perl script and snippets of code.
scriptnull/compilex
[DEPRECATED] compilex is a node.js library which is used to build online code compiler/interpreter websites and webservices.
go2uvm/sva_traces
Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors
BXYMartin/MIPS-CPU
Xilinx Project for MIPS CPU
minhhn2910/FPGA-RISC-MCU
Simple RISC MCU written on Verilog and Compiler for that MCU.
alchemist231/ARM-pipelined-processor-core-Verilog-
ARM pipelined processor core ( Verilog )
jomonkjoy/Low-Speed-Controllers
I2C, SPI, UART memory bridge
Aceic/BLE-VER-1
BLE-Version-1
regmeg/AES128_ASIC
ameyjain/8-bit-Microprocessor
8-bit microprocessor using Verilog
cleichner/hlfsm-synth
A compiler from a C-like language to FSMs in Verilog
jomonkjoy/FFT-Computation
Fast Fourier Transform (FFT) algorithm computes the discrete Fourier transform (DFT) of a sequence, or its inverse (IFFT)
jomonkjoy/SDRAM-Controller
EDEC STANDARD Double Data Rate (DDR) SDRAM Specification
lz1/Lz1_32bits_RISC_CPU
Basic RISC 32 bits CPU
PanielDan/Candy_Crush_Verilog
A modified version of the popular game Candy Crush in Verilog. This is programed for a Nexsys 3 Spartan 6 FPGA with a VGA connection. You can compile all these files in Xilinx and upload the bit file to program into an FPGA