/Dadda_multiplier

A 16-bit dadda multiplier using a 4:2 compressor

Primary LanguageVerilogMIT LicenseMIT

Dadda_multiplier

This is a 16-bit dadda multiplier using a 4:2 compressor modelled in Verilog HDL.

Usage

iverilog dadda_tb.v

TODO

  • Readability of code needs to be improved. Variable names, and the like, need to be changed. Basically, entire program needs to be modified significantly to improve readability.
  • 32 bit version of the same.