Pinned Repositories
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
Awesome-CV
Awesome CV is LaTeX template for your outstanding job application
BiLLM
BiLLM: Pushing the Limit of Post-Training Quantization for LLMs
BinaryViT
BinaryViT: Pushing Binary Vision Transformers Towards Convolutional Models
Building-Accelerated-Applications-with-Vitis
Support material for the Building Accelerated Applications with Vitis webinar series
CHaiDNN
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
CNN-using-HLS
Convolutional Neural Network Using High Level Synthesis
deepeda
phax
arash1902's Repositories
arash1902/deepeda
arash1902/AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
arash1902/BiLLM
BiLLM: Pushing the Limit of Post-Training Quantization for LLMs
arash1902/BinaryViT
BinaryViT: Pushing Binary Vision Transformers Towards Convolutional Models
arash1902/Building-Accelerated-Applications-with-Vitis
Support material for the Building Accelerated Applications with Vitis webinar series
arash1902/CNN-using-HLS
Convolutional Neural Network Using High Level Synthesis
arash1902/CSCI_596_Final_Project
CSCI 596 Final Project
arash1902/dMazeRunner
dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
arash1902/finn
Dataflow compiler for QNN inference on FPGAs
arash1902/FlexCNN
arash1902/FracBNN
arash1902/ftdnn
FPGA-tailored DNN
arash1902/gemmini
Berkeley's Systolic Array Generator
arash1902/Grain-tracking-algorithm-based-on-highly-parallel-DBSCAN
arash1902/HiSparse
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
arash1902/hlslib
A collection of extensions for Vivado HLS and Intel FPGA OpenCL to improve developer quality of life.
arash1902/LogicRegression
arash1902/LPCV2021_Winner_Solution
arash1902/LUTNet
arash1902/MemTorch
A Simulation Framework for Memristive Deep Learning Systems
arash1902/MNSIM-2.0
A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems
arash1902/Nerual-Network-Acceleration-1
Neural Network Acceleration such as ASIC, FPGA, GPU, and PIM
arash1902/Provable-Data-Subset-Selection-For-Efficient-Neural-Network-Training
Provable Data Subset Selection For Efficient Neural Network Training
arash1902/RVAE
Robust variational autoencoders (RVAE)
arash1902/SSR
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
arash1902/timeloop
arash1902/timeloop-accelergy-exercises
Exercises for exploring the Timeloop and Accelergy tools
arash1902/timeloop-accelergy-tutorial
Docker container with tools for the Timeloop/Accelergy tutorial
arash1902/udf_op
arash1902/Vitis_Libraries
Vitis Libraries