a simplified pipelined MIPS microprocessor using HDL
This a pipeline processor which can execute MIPS instructions with verilog.
A whole CPU module is implemented, including the clock, instruction memory, registers, ALU, data memory and control unit. It defines the MIPS instruction and build the data path in a verilog file and test the MIPS instructions in the test file.
For detailed information, please check "ReportForCPU.pdf".