Pinned Repositories
auriga
cephes
Mirror of the Cephes C source for reference
Clock-module
Implementation of Clock on Znyq 7
cluelib
A generic class library in SystemVerilog
cocotb
Coroutine Co-simulation Test Bench
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cpp-cheatsheet
Modern C++ Cheatsheet
crypto-algorithms
Basic implementations of standard cryptography algorithms, like AES and SHA-1.
embeddedsw
Xilinx Embedded Software (embeddedsw) Development
Rufous
Rofous RISC-V based Microcontroller
arkhan91's Repositories
arkhan91/Rufous
Rofous RISC-V based Microcontroller
arkhan91/auriga
arkhan91/Clock-module
Implementation of Clock on Znyq 7
arkhan91/cluelib
A generic class library in SystemVerilog
arkhan91/cocotb
Coroutine Co-simulation Test Bench
arkhan91/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
arkhan91/cpp-cheatsheet
Modern C++ Cheatsheet
arkhan91/crypto-algorithms
Basic implementations of standard cryptography algorithms, like AES and SHA-1.
arkhan91/embeddedsw
Xilinx Embedded Software (embeddedsw) Development
arkhan91/git-cheat-sheet-tall
A cheat sheet for Git workflows.
arkhan91/hdl_lib
arkhan91/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
arkhan91/IDEA_Algorithm
Only Simmulation of IDEA Algortihm
arkhan91/kerncraft
Loop Kernel Analysis and Performance Modeling Toolkit
arkhan91/miaow
An open source GPU based off of the AMD Southern Islands ISA.
arkhan91/RISC-V-TLM
RISC-V SystemC-TLM simulator
arkhan91/riscv-isa-sim
Spike, a RISC-V ISA Simulator
arkhan91/rocket-chip
Rocket Chip Generator
arkhan91/rocket-rocc-examples
Tests for example Rocket Custom Coprocessors
arkhan91/style-guides
lowRISC Style Guides
arkhan91/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
arkhan91/SystemVerilogAssertions
Examples and reference for System Verilog Assertions
arkhan91/USTC-RVSoC
FPGA-based RISC-V CPU+SoC.
arkhan91/VSCode-SystemVerilog
SystemVerilog support in VS Code
arkhan91/vscode-systemverilog-support
[deprecated]use mshr-h/vscode-verilog-hdl-support
arkhan91/vscode-verilog-hdl-support
Verilog HDL/SystemVerilog support for VS Code
arkhan91/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
arkhan91/wavedrom
:ocean: Digital timing diagram rendering engine
arkhan91/yubico-c-client
Yubico C client library
arkhan91/Zynq_7000_SDK