Please register for IEEE Cluster here to join the EA-HPC workshop event on September 7th. We will use a Zoom link through the IEEE Cluster RDMobile application as well as the IEEE Cluster Slack channel
EAHPC-2021 will be running as a live, recorded event on 7 September 2021. The login details will be provided via the IEEE Cluster conference to registered attendees.
| Time (PDT) | Presenter | Talk Title (Click for Slides) | Paper Coauthors |
|---|---|---|---|
| 7:00-7:10 AM | Jeffrey Young | Workshop Introduction | |
| Session Chair: Tony Curtis | |||
| 7:10-7:35 | Jens Domke | A64FX – Your Compiler You Must Decide! (Alternate Slide Link) | |
| 7:35-8:00 | Miwako Tsuji | Performance Evaluation and Analysis of A64FX many-core Processor for the Fiber Miniapp Suite | Mitsuhisa Sato |
| 8:00-8:10 | BREAK | ||
| Session Chair: Mitsuhisa Sato | |||
| 8:10-8:35 | Jérôme Gurhem | Sequences of Sparse Matrix-Vector Multiplication on Fugaku’s A64FX processors | Maxence Vandromme, Miwako Tsuji, Serge G. Petiton, Mitsuhisa Sato |
| 8:35-9:00 | Md Abdullah Shahneous Bari, Eva Siegmann | A64FX performance: experience on Ookami | Barbara Chapman, Anthony Curtis, Robert J. Harrison, Nikolay A. Simakov, Matthew D. Jones |
| 9:00-9:10 | BREAK | ||
| Session Chair: Sadaf Alam | |||
| 9:10-9:35 | Fabio Banchelli | Cluster of emerging technology: evaluation of a production HPC system based on A64FX | David Vicente, Marta Garcia-Gasulla, Filippo Mantovani |
| 9:35-10:00 | Sarat Sreepathi | Early Evaluation of Fugaku A64FX Architecture Using Climate Workloads (Alternate link) | Mark Taylor |
| 10:00-10:30 | General discussion and feedback on what is needed for Arm HPC |
Submissions via EasyChair EAHPC-2021.
As part of the IEEE Cluster 2021 conference we will host a 1/2 day Arm workshop on evaluating emerging, server-class, Arm technology.
The IEEE Cluster conference will be hosted this year between the 7th and 10th of September. Due to COVID-19 this workshop will be hosted virtually on the 7th of September.
This workshop focuses on the porting and optimization of scientific and high-performance workloads to the Arm architecture. The last few years have seen an explosion of 64-bit Arm based processors targeted towards server and infrastructure workloads – often with a specialization towards a specific domain – such as HPC, cloud and machine learning. Arm’s new Neoverse reference N1 core design has become the foundation for a number of emerging processors such as Amazon’s 64-core Graviton2 and Ampere’s 80-core Altra, with the EPI project incorporating the successor design into SiPearl’s Rhea chip. Furthermore, architecture licenses are being exploited to design and manufacture bespoke solutions such as Marvell’s ThunderX line of processors and Fujitsu’s A64FX chip.
One of the most important additions to the Arm instruction set has been SVE – the Scalable Vector Extension – an architectural extension containing a comprehensive set of vector length agnostic vectorization instructions. Making its debut in the A64FX processor, these vector instructions present a paradigm shift for application developers.
In this workshop we invite papers on the porting and, if available, optimization of high-performance workloads for this new generation of Arm-based processors. We welcome performance optimization studies either through access to real hardware or via simulation/emulation frameworks, for both SVE and otherwise.
Content specifically focuses on HPC, edge, AI, and everything in between. Specifically, we will include talks related to applications and cross-over/emerging application areas such as machine learning, deep learning, bioinformatics, and analytics; all on Arm-compatible platforms.
This workshop is the second iteration of EAHPC and is a proceedings-based workshop that is closely related to the series of workshops organized at ISC, SC and the Arm Research Summit by groups like the Arm HPC User Group (AHUG).
- Data, Storage & Visualization
- HPC Applications
- Performance Analysis
- SVE Vectorisation analysis
- Programming Models & Systems Software
- Artificial Intelligence and Machine Learning
- Performance Modeling & Measurement
- Emerging Technologies
Submissions will be taken through EasyChair at the following link: EAHPC-2021.
Accepted papers will be included in the IEEE Cluster 2021 conference proceedings.
All submissions must be made in IEEE Format.
- Full Papers: 8 pages (+ 2 additional pages)
- Short Papers: 4 pages (+ 1 additional page)
Submission Deadline: 13th July (AoE)
Final and Updated Submission Deadline: 16th July (AoE)
Author Notification: July 28th (AoE)
Camera Ready: July 30th (AoE)
- Dr. Sadaf Alam (CSCS)
- Dr. Tony Curtis (Stonybrook)
- Dr. Jeffrey Young (Georgia Tech)
- Prof. Mitsuhisa Sato (RIKEN)
** Special thanks to Steve Poole (LANL) for help in workshop submission and initial organization! **
- Jonathan Beard, Arm
- Mark Bull, The University of Edinburgh Marc Casas, BSC
- Guillaume Colin De Verdiere, CEA/DAM
- Miguel Cruz, INESC-ID
- Jens Domke, RIKEN R-CCS
- José Gracia, High-Performance Computing Center Stuttgart
- Adrian Jackson, The University of Edinburgh
- Sylvain Jubertie, Laboratoire d'Informatique Fondamentale d'Orleans
- Yuetsu Kodama, RIKEN R-CCS
- John Linford, Arm
- Will Lovett, Arm
- Fabrizio Magugliani, E4
- Filippo Mantovani, Barcelona Supercomputing Center
- Jean-François Mehaut, Laboratoire LIG
- Miquel Moreto, UPC-BSC
- Tetsuya Odajima, RIKEN R-CCS
- Takahiro Ogura, RIKEN
- Kevin Pedretti, Sandia National Labs
- Marc Perache, CEA,DAM,DIF
- Lucas Pettey, Arm
- Dirk Pleiter, KTH
- Andrei Poenaru, University of Bristol
- Phil Ridley, Arm
- Daniel Ruiz-Munoz, Arm
- Roxana Rusitoru, Arm
- Nathan Sircombe, Arm
- Shinji Sumimoto, Fujitsu Laboratories
- Srinath Vadlamani, Arm
- Michele Weiland, The University of Edinburgh
Jeff Young (jyoung9@gatech.edu)