arturum1

Pinned Repositories

iob-axi
Language:Verilog00
iob-axis
Language:Verilog00
iob-cache
Verilog configurable cache
Language:Verilog00
iob-clint
Language:C0 0 00
iob-dma
Language:Verilog00
iob-eth
Basic Verilog Ethernet core and C driver functions
Language:Verilog00
iob-gpio
Language:Tcl0 0 00
iob-ila
Language:Verilog0 0 00
iob-lib
Language:Verilog00
iob-linux
Language:Python00

arturum1's Repositories

arturum1/iob-axi
Language:Verilog00
arturum1/iob-axis
Language:Verilog00
arturum1/iob-cache
Verilog configurable cache
Language:Verilog00
arturum1/iob-clint
Language:C0 0 00
arturum1/iob-dma
Language:Verilog00
arturum1/iob-eth
Basic Verilog Ethernet core and C driver functions
Language:Verilog00
arturum1/iob-gpio
Language:Tcl0 0 00
arturum1/iob-ila
Language:Verilog0 0 00
arturum1/iob-lib
Language:Verilog00
arturum1/iob-linux
Language:Python00
arturum1/iob-pfsm
Language:Python
arturum1/iob-picorv32
IOb_SoC version of the Picorv32 RISC-V Verilog IP core
Language:Verilog
arturum1/iob-plic
Language:C
arturum1/iob-regfileif
Language:Python
arturum1/iob-soc
RISC-V System on Chip Template Based on the picorv32 Processor
Language:Python
arturum1/iob-soc-opencryptohw
SoC to run the program in software with or without acceleration using VERSAT2.0
Language:Verilog
arturum1/iob-soc-opencryptolinux
Language:C
arturum1/iob-soc-sut
Language:C
arturum1/iob-soc-tester
arturum1/iob-spi
Language:Verilog0 0
arturum1/iob-timer
Simple Timer IP Core in Verilog
Language:C
arturum1/iob-uart
Language:C
arturum1/iob-uart16550
Language:Verilog
arturum1/iob-vexriscv
Language:Verilog
arturum1/py2hwsw
a Python framework for managing embedded HW/SW projects
Language:Python
arturum1/verilog-axi
Verilog AXI components for FPGA implementation
Language:Verilog