vsdworks

This repository contains all the information required for the physical design flow of your IPs or SOCs, using qflow and other open-source tools. It was created during the "Beginner Physical Design using Open-Source EDA Tools" .

TABLE OF CONTENT

1. DAY-1

PART-1 (INTERACTION WITH COMPUTER)
- INTRODUCTION TO QFN-48
- INTRODUCTION TO RISC-V
- FROM S/W TO H/W APPLICATIONS
PART-2 (SOC DESIGN AND OPENLANE)
- INTRODUCTION TO ALL OPEN SOURCE DEGITAL ASIC DESIGN
- SIMPLIFIED RLT2GDS FLOW
- INTRODUCTION TO OPENLANE AND STRIVE CHIPSET
- INTRODUCTION TO OPENLAEN DETAILED ASIC DESIGN FLOW
PART-3 (GET FAMILIAR WITH OPEN SOURCE EDA)
- OPENLADE DIRECTORY STRUCTURE IN DETAILS
- DESIGN PREPARATION SETUP
- RUN SYNTHESYS
- OPENLANE PROJ GIT LINK DESCRIPTION
- STEPS TO CHARACTERISE THE RESULT OF SYNTHESIS

DAY-2

DAY-1

PART-1 (INTERACTION WITH COMPUTER)

1. INTRODUCTION TO QFN-48

PACKAGE QFN-48

The package are protective layer where ICs are put into to easy handing and assembling onto printed ciruite board to protect devices from damage.

Here, QFN-48 means Quad Flat No-leads which have 48 pins and surface_mount. A wide variety of electronic packages exist, including through-hole packages, surface mount packages, chip carriers, pin grid arrays, flat packages, and ball grid arrays. Using these small packages we can place IC to a circuit board.

These are used in various applications as follows,

Automotive
Consumer electronics
Industrial and powe applocations ...etc.

The core is placed in the middle of the quad flat package. Here below is how the chip placed in the middle of the package looks like

IC is the intergrated circuit which consist of millions of transistors, cpacitors, resigtors inside a semiconductor chip. They comes in veriety of size and pakages.

SOC - System on Chip is kind of IC which has the capability of combining functional elemnts of many electronic device on a single chip. It may constist of CPU, Memeory, inputs, outputs, ICs, IPs and other functional elements integrated init. SOC is used in multiple computing task, we can widely see in mobiles, laptops, tablets, AI devices etc.

The chip is madeup of core and die area.

Die is the semiconductin_material(specimen) on which caore(fundamental logic circuit) is fabricated.

Core is the section of chip where the fundamental logic of the design is placed.

The fabrication of the chip is done on the silicon wafer which are usually of 9 inch to 12 inch in diameter. Then, this wafer is cutted into pieces. Each piece has similar funtionality of the fundamental logic called Die.

We can make external connection by placing Pads on the rectangualer metal patches as in above fig.

2. INTRODUCTION TO RISC-V

RISC-V stands as a public, open-source specification for an Instruction Set Architecture (ISA) based on Reduced Instruction Set Computer prinnciples, setting it apart from the proprietary ISAs such as x86, typically found in personal computers, and ARM, commonly used in mobile devices. Unlike many ISAs that are bound by proprietary standards, RISC-V is accessible under licenses that are free of charge, giving it a significant advantage over its commercial counterparts. It’s characterized by its simplicity, stability, and compact standard base, while offering extendable ISA support. This has been instrumental in enhancing the adaptability, scalability, extensibility, and modular nature of chip designs.

3. FROM S/W TO H/W APPLICATIONS

Assembly language is the bridge betweeen s/w and h/w. Different software and applications runs in different language programs(ex:- C, C++, Java, pyhton ...etc). Hardware cannot understand these lanuguages therefore we use special program like comiler and assembler to convert the instuctions in different languages to the targeted assembly language.

PART-2 (SOC DESIGN AND OPENLANE)

1. INTRODUCTION TO ALL OPEN SOURCE DEGITAL ASIC DESIGN

Some of the open sources we can use for,

RTL Designs
- libracores.org
- opencores.org
- github.com
EDA tools
- Qflow
- OpenRoad
- OpenLane
PDK data
- Google + skywater = foss 130nm PDK

PKD: Process Desin Kit is a collection of files used to model fabrication process by the EDA tools to design an IC.

This is the interface between fabrication and designers

The PDK includes:

PDRs: process design rules contained in DRC, LVS, PEX files.

Device Models.

Digital STD_Cell libs.

I/O libs.

2. SIMPLIFIED RLT2GDS FLOW

Logic Synthesis

no.	Description	tool
i	RTL synthesis using	yosys
ii	Technology mapping using	abc
iii	STA reports using	OpenSTA

Floor Plan

no.	Description	tool
i	To implement core area	init_fp
ii	To place input,output ports and macros	ioplacer
iii	To geerate the power description n/w	pdn
iv	To insert welltap and Decap cells(physical only cells)	tapcell

Placement

no.	Description	tool
i	To perform Global Placement	RePlace
ii	To Perform Design Optimization	Resizer
iii	To perform Timing Optimization	OpenPhySyn
iv	To Perfrom Detailed Placement	OpenDP

CTS

no.	Description	tool
i	To synthesize the CLK distribution n/w	Triton CTS

Routing

no.	Description	tool
i	To perform Global rouitng	FastRoute
ii	To perform detailed routing	TritonRoute
iii	To Perform SPEF extraction	SPEF-Extraction

STA

no.	Description	tool
i	To get STA reports	OpenSTA

GDSII Generation

no.	Description	tool
i	to perform final GDSII layout file from routed def	magic

Checks

no.	Description	tool
i	To perform DRC checks and Antenna Checks	Magic
ii	To perform LVS checks	NetGen

3. INTRODUCTION TO OPENLANE AND STRIVE CHIPSET

4. INTRODUCTION TO OPENLAEN DETAILED ASIC DESIGN FLOW

PART-3 (GET FAMILIAR WITH OPEN SOURCE EDA)

1. OPENLANE DIRECTORY STRUCTURE IN DETAILS

Importent file in openlane_working_dir

pdk file
openlane

The PDK we are usign here is Skywater130nm which is recently made as opensource. Openlane is built arround this pdk.

Firest lets see PDK file:

ALL the files present in these pdk files are shown in the above directory structure.

The silicon foundry files i.e.,skywater130nm or any of the foundry files made to use in the commerrtial eda tools(Paid version) rather than opensource eda tools. This open_pdks used to avoid this problem by converting the files from commertial levl to opensource tool(for example like magic, netgen...etc) usable.

Sky130A is the foundry file that made opensource eda compatible.

file	description	contents
libs.ref	it is specific to tecchnology. Here we are focusing on Sky130_fd_sc_hd
libs.tech	it is specific to tool

sky130_fd_sc_hd :

The file name abrivates as follows,

fd --> foundry
sc --> std_cells
hd --> high dencity

these are the files we can find inside the sky130_fd_sc_hd

2. DESIGN PREPARATION SETUP

openlane

openlane is a silicon implimtntation platform that supports open-source tools such as yosys, Openroad, Macgic, Klayout along with other opensource and proprietary utilities.

These are the files present in openlane

The list of main commands we use here are:

note:- the commads from 3 to 14 can be put into a <file_name> and we can pass it to "flow.tcl" i.e, > ./flow.tcl -interactive -file <file_name>

Design file

picorv32a is the Design we are using here. we can also create other desig aswell in the design folder of openlane.

Some list of designs we will get in design is shown in below:

The files included in the picorv32a is as follows:

note:- here config.tcl contains information about:

design name

path to sdc and .v

clock_period, cloc_port, clock_net

DOCKER

First we need to get inside docker_build using command docker And get the docker into interactive mode.

we should be in interactive mode ohter wise it will excicute full flow.

./flow.tcl -interactive

we need to include all the files required to run the flow

package require openlane 0.9

Design setup stage:

When we run prep -design picorv32a a run file with todays date will be created inside the Picorv32a>runs>dd-mm_hr-min

At this point we can see multiple folders and files are created inside the 27-04_08-06 file. But most of them are empty.

Step by step each files will generated with report files inside these files.

Next we will start our synthesis

3. RUN SYNTHESIS

run_synthesisThis will run the yosys and abc synthesis.

4. OPENLANE PROJ GIT LINK DESCRIPTION

https://github.com.efabless/openlane

5. STEPS TO CHARACTERISE THE RESULT OF SYNTHESIS

After synthesis report files are generated inside the synthesis folder present in runs. we can see the report mentioned above in these folders, as shown below.

DAY-2

PART 1. Chip floor planning considerations

1. Utilization factor and Aspect ratio

6. STEPS TO RUN FLOORPLAN

Before sunning the floor plan just have a glan on README.md file in openlane/configuration directory.

open openlane/configuration/floorplan.tcl where we can see default parameter set for floorplan by openlane.

here we need to give more preority to these files.

7. steps to view floorplan

8. Review Floorplan in magic

we can get info of an object by selecting it and asking >what in teckon as shown below.

PART 2. Library Binding and Placement

Congestion aware placement

The next stage after the floorplan is placement to see placement in magic tools:

We can see All the std_cells placed in std_cells rows. All the physical only cells also place.

PART 3. Cell design and characterization flow

PART 4. General timing charactorization parameters

Steps to Disply std_cells Uisng Magic tool

first we need to get the technology file from sky130A pdk folder, to the vsdstdcelldesign folder.
now give magic tool command to display the cell

magic -T sky130A.tech sky130_inv.mag
The inevertor std_cell will be displayed as below.

Introduction to sky130 basic layers and Lef using inerter

we can use tkcon to get the infrmation about the cell layers by giving command what.

Creat std cell layout and extract SPICE netlist

first we need to create spice file for our Invertor. tcl ext2spice cthresh 0 rthresh 0 ext2spice this will create new .spice file in our vsdstdcelldesign file

Grids are used for easy measure. box in tckon to get the measurment of the grid

Make required modification in spice file.

we need to ru this in ngspice using ngsipce <source file name>

Now to see plot use command in spice as below:

plot y vs time a

this is our transiant response

Now we need to charectorize the cell. means we need to derive value of 4 parameters.

value of rise transition diff b/w x0 should give raise time:

(2.19701e-09) - (2.15231e-09) = 0.0447ns
value of fall transition

(4.06584e-9) - (4.0401e-9) = 0.02574ns
fall cell delay

(4.05284e-9)-(4.05052e-9)=0.00228ns
rise cell delay

(2.18e-9) - (2.15e-9) = 0.03ns

Instruction to sky130 pdk's and steps to download

download the files from git wget http://opencircuitdesign.com/open_pdks/archive/drc_tests.tg

To open the magic tool use:

magic -d XR

then open metal3.meg file

To make a via : select a area > select the maetal layer > set the via using cif see VIA2

incorrect poly.9

to correct the error we need to go to sky130.tech file

add the spacing

then, source the tech file again.

Lab challenge to c=describe the DRC error as geometrical construct

vendor drc rules

modified nwell under vendor drc rules

style drc modified style drc

problem is solved by adding nsubstratecontact

Day 4 Pre layout analysis and importance of good clock tree

Steps to convert grid info to track info

first objective is to extract lef file from .mag file

Then, the extracted lef file is plugged into picorv32flow

these are teck info, used during routing stage.

li1 is the locali we can see in lable A and Y.

now we have converted Grid definition according to track.

second objective is to convert magic layout to std cell lef

width of the std cells must be odd multiple of x pitch. same goes for height also.

now we can see how to convert label to ports.

this is how we can create the ports usinf label for A. similerly we can do for all the ports. we need to be carefull while attaching to layer. In label-A and Y, the attach to layer is locali . But for others it may be metal1, metal2 ..etc. like that.

save the layout with our own costum name. i have given sky130_vsdinv.mag.

After creating the sky13_vsdinv.mag open it in magic tool. do lef write, wwhich create leaf file is the same directory.

lef file contains the modifications we have done.

Now we have to move these files to our design src files. So that all our design files present in a single group.

Now one more fiel we need to cp is

after copiying all files our src file will look like this

now that we have added the file, we have to run the reguler flow commands i.e., from docker to synthesis.. floorplan...etc.

run_synthesis

To improve the timing and run synthesis ``tcl

prep -design picorv32a -tag 24-03_10-03 -overwrite

set lefs [glob $::env(DESIGN_DIR)/src/*.lef] add_lefs -src $lefs

echo $::env(SYNTH_STRATEGY)

set ::env(SYNTH_STRATEGY) "DELAY 3"

echo $::env(SYNTH_BUFFERING)

echo $::env(SYNTH_SIZING)

set ::env(SYNTH_SIZING) 1

echo $::env(SYNTH_DRIVING_CELL)

run_synthesis ``

Check if vsd_inverter is added after the floorplan stage. Check layout after the placement_stage. the above can be seen in merged.lef file in runs/03-5_12_15/tmp/merged.lef.

after running the run_placement, open the placement using magic tool. Then search for our sky130_vsdinv by zooming in. the 'adutment' is to ensure the power and ground is shared between cells.

when we expand the vsdinv cell we can see the connection between metal layers of our vsdinv cell and the abuted cells.

To configure OpenSTA for post timing analysis

create a file named pre_sta.conf in openlane directory.

We can see our cell's pin capacitance in *typical.lib file

we have to create a file called my_base.scd in src file of design.

the above my_base.scd is written by taking the reference of base.sdc fiel in openlane scripts.

this the file where we are going to do STA.

use command:

sta pre_sta.conf

we can get the report of the nets using:

report_net -connections net_instance_name replace_cell instace lib_cell report_checks -fileds {net cap slew input_pins} -digits 4

by replacing the currect cell we can reduce the slack and get the report again.

After reducing the slack value to 0 or almost 0. we should rewite the old design.v file with the newly modified one. For that we use write command with path to design file with name, which will replace the old design file with new one.

%write_verilog /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/03-05_12-25/results/synthesis/picorv32a.synthesis.v

then we can exit OpenSTA

After rewriting the netlist in openSTA we shouldnt run the synthesis again bcz it will create new netlist.

Therefore now next step is to run_floorplan. So that it takes the updated netlist.

run_placement

Run CTS

After getting to placement stage of updated netlist we need to run CTS.

run_cts

this may take some time to run. then it will create cts file in synthesis file inside results.

To know what are the arguments the our cts will check we need to go for cts.tcl in command file of openlane. here the main thing we need to look is for openroad.

these are the tcl files we can see in the openroad.

Here we cannot see the synthesis part bcz openlane normally dosnt involve the synthesis in the process if we look into the openlane flow.

Post-CTS OpenROAD timing analysis.

The next stages are power distribution and Routing. Both will use the .def file.

Since openlace is integrated with openlane. we can access openroad in the openlane. Now we can do Timing analysis here itself.

`` openroad

read_lef /openLANE_flow/designs/picorv32a/runs/30-04_05-57/tmp/merged.lef

read_def /openLANE_flow/designs/picorv32a/runs/30-04_05-57/results/cts/picorv32a.cts.def

write_db pico_cts.db

read_db pico_cts.db

read_verilog /openLANE_flow/designs/picorv32a/runs/30-04_05-57/results/synthesis/picorv32a.synthesis_cts.v

read_liberty $::env(LIB_SYNTH_COMPLETE)

link_design picorv32a

read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc

set_propagated_clock [all_clocks]

help report_checks

report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4

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