/snake-verilog

This program is written in verilog .

Primary LanguageVHDL

Build Status Coverage Status

Snake with Verilog

This program is written in verilog and can be synthesied on Spartan-III FPGA . The x-y axis is dynamic and changes according to snake head direction . Snake tries to eat the target in the best way and it can handle its body . The sreen also has 4 barriers that snake will handle them .

Snake beginning size : 2 blocks 
Number of targets : 15 
Number of barriers : 4 

Block scale : 10 * 10 pixels

Sample picture and video

Screen Capture

Team

> Arya Khaligh  [BartarArya@gmail.com] 
> Hadi Hosseini [hadi.hosseini0171@gmail.com]

Under supervision Jamileh Behzadi [jamileh_behzadi@aut.ac.ir]