Pinned Repositories
gem5_gt
NoCRouter
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
chiplet_code
chiplet_mapping_ir
clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
e203_hbirdv2
The Ultra-Low Power RISC-V Core
ethernet_10ge_mac_SV_tb
SystemVerilog testbench for an Ethernet 10GE MAC core
gamma
gem5
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.
hetero_gem5
aserenate's Repositories
aserenate/NoCRouter
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
aserenate/wxy_chiplet_code
aserenate/chiplet_code
aserenate/HLSinf
High-Level Synthesis inference accelerator for FPGAs
aserenate/multicast_router
aserenate/timeloop
Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.
aserenate/maestro
An analytical cost model evaluating DNN mappings (dataflows and tiling).
aserenate/chiplet_mapping_ir
aserenate/gem5
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.
aserenate/hetero_gem5
aserenate/openocd_riscv
Spen's Official OpenOCD Mirror
aserenate/e203_hbirdv2
The Ultra-Low Power RISC-V Core
aserenate/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
aserenate/gamma
aserenate/vimplus
:rocket:An automatic configuration program for vim
aserenate/gem5_gt
aserenate/UART
UART design in SV and verification using UVM and SV
aserenate/osc10e
Source code for the 10th edition of Operating System Concepts
aserenate/ethernet_10ge_mac_SV_tb
SystemVerilog testbench for an Ethernet 10GE MAC core