Pinned Repositories
ashmanskas.github.io
cocotb_regsync_vs_afifo
first prototype and quick test of two-clock "unfifo" for Paul
mcu
Master Coincidence Unit for BPET system
microzed_adrian
sample microzed project for Adrian
nbpublic
wja public jupyter notebooks
PMTDivider
recipe
simple recipe-list web page organized using emacs org-mode
rocstar_hdf5
hdf5/hfpy I/O throughput test
rsnb
jupyter notebooks for rocstar board
try_cocotb_120
try cocotb 1.2.0 with ius and questa simulators
ashmanskas's Repositories
ashmanskas/mcu
Master Coincidence Unit for BPET system
ashmanskas/ashmanskas.github.io
ashmanskas/cocotb_regsync_vs_afifo
first prototype and quick test of two-clock "unfifo" for Paul
ashmanskas/microzed_adrian
sample microzed project for Adrian
ashmanskas/nbpublic
wja public jupyter notebooks
ashmanskas/PMTDivider
ashmanskas/recipe
simple recipe-list web page organized using emacs org-mode
ashmanskas/rocstar_hdf5
hdf5/hfpy I/O throughput test
ashmanskas/rsnb
jupyter notebooks for rocstar board
ashmanskas/try_cocotb_120
try cocotb 1.2.0 with ius and questa simulators
ashmanskas/uzed_dma
ashmanskas/verilog_examples
A few examples of Verilog that is coded in a way that I intend to be easy to follow