asicguy

axi-bfm

Automatically exported from code.google.com/p/axi-bfm

axi4_bfm

AXI 4 BFM library compatible with the Cadence libraries distributed by Xilinx

crash

Cognitive Radio Accelerated with Software and Hardware

DisplayPort_Verilog

A Verilog implementation of DisplayPort protocol for FPGAs

ecc-generator

Automatically exported from code.google.com/p/ecc-generator

gplgpu

GPL v3 2D/3D graphics engine in verilog

miaow

An open source GPU based off of the AMD Southern Islands ISA.

Minimig-AGA_MiSTer

spacex_uart

Project and presentation for SpaceX Application

verilog-ethernet

Verilog Ethernet components for FPGA implementation

asicguy/Minimig-AGA_MiSTer

asicguy/verilog-ethernet

Verilog Ethernet components for FPGA implementation

asicguy/xceed_se-306_48

HDL for xceed clone board

asicguy/alice5

SPIR-V fragment shader GPU core based on RISC-V

asicguy/ao486_MiSTer

ao486 port for MiSTer

asicguy/Apple-II_MiSTer

Apple II+ for MiSTer

asicguy/arcade-foodfight

FPGA foodfight arcade game in verilog

asicguy/Atari7800_MiSTer

Atari 7800 for MiSTer

asicguy/coco3_MiSTer

Coco3 port to Mister

asicguy/Custom_Part_Data_Files

Xilinx PCIe to MIG DDR4 example designs and custom part data files

asicguy/fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

asicguy/fx68k

FX68K 68000 cycle accurate SystemVerilog core

asicguy/GBA_MiSTer

GBA for MiSTer

asicguy/HT1080Z_MiSTer

port of HT1080Z to MiSTer (Tandy TRS-80 Model I)

asicguy/MacPlus_MiSTer

Macintosh Plus for MiSTer

asicguy/macsehw

Macintosh SE Hardware Designs

asicguy/polyphony

3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.

asicguy/Projects

asicguy/vortex

asicguy/BBCMicro_MiSTer

BBC Micro B and Master 128K for MiSTer

asicguy/biriscv

32-bit Superscalar RISC-V CPU

asicguy/croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

asicguy/cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

asicguy/MiSTeX-boards

Core generation scripts for various FPGA boards

asicguy/neorv32

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

asicguy/openc910

OpenXuantie - OpenC910 Core

asicguy/RISCV-FiveStage

Marginally better than redstone

asicguy/Vitis_Hero

asicguy/wolv-z7

Wolv Z7 is a RISC-V CPU core with floating point unit

asicguy/yrv-sv

Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.