Experiments in bringing up SKY130 MPW-3 chips from the initial tapeout in November 2021. Similarly to MPW-1, the standardized "Caravel" padframe used in this tapeout had hold-time violations between
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Characterization PCB Schematic
- Independent voltage regulators for padframe and core (with non-volatile memory)
- DS1077LU-50 clock generator with 50kHz - 50MHz output frequency + non-volatile memory
- MCP23017 GPIO expanders for scanning chip I/Os
- MCP1319 reset supervisor
- MicroMod-style socket for Caravel chip breakout
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FTDI Breakout Schematic
- Connects characterization PCB to FT232RL for UART access over USB
- Includes LEDs, switches, and SPI FRAM for use with picoRF0 CPU
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VGA Breakout Schematic
- Breaks out infinite-runner game and pong game to a 2-bit VGA DAC
- Includes buffer chips for
boards/
- KiCAD design files for breakout PCBsparts/
- I/O characterization results for several diesscripts/i2c_iface.py
- Script for interfacing with the voltage regulators, clock generator, and GPIO expanders on the characterization boardprograms/
- Programs for running on the Caravel processor for the different applicationsaes_test.c
- Test the AES core on crypto-accelerator-chip-v2 designgpio_config_io_dino.py
- GPIO configuration for the VGA runner gamegpio_config_io_pong.py
- GPIO configuration for the VGA pong gamepicorf0_test.c
- Test program for the picoRF0 custom CPU coreread_ident.c
- Reads the ROM identifier and build number in the SHA and AES coressha256_test.c
- Test the SHA256 core with some test vectorsspi_fram.c
- Test program for using the Caravel SPI master to interface with an FRAM chipuart_working.c
- Workaround for UART RX on MPW-3 Caravel