asm2750/Neopixel_TX_Core

Issues

• Write proper test bench for verilog code

  #6 opened 10 years ago by asm2750
  0

• Improve MOJO demo

  #4 opened 10 years ago by asm2750
  0

• Add SPI interface to core for ease of use.

  #5 opened 10 years ago by asm2750
  0

• Add documentation

  #3 opened 10 years ago by asm2750
  0

• Support Altera and Xilinx block memories in FIFO

  #2 opened 10 years ago by asm2750
  0

• Altera quartus II example is needed

  #1 opened 10 years ago by asm2750
  0