Final Hunter CPU Ahmed Wael Fahmy 900160127 Habiba Gamal 900151007 Ali El-Said 900150264 We did not find any limitations or issues with our Datapath block diagram or out Verilog HDL code through our testing. Note: Memory reads from a file. Memory supports unaligned operations, and is little endian(note when testing).
awael/RISC-V-Implementation
This is a Verilog Implementation of RISC-V CPU that implements RV32I and RV16I and supports interrupt handling and some CSR instuctions and registers
Verilog